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hitachi single-chip microcomputer h8/534, h8/536 hd6475348r, hd6435348r hd6475368r, hd6435368r hd6475348s, hd6435348s hd6475368s, hd6435368s hardware manual ade-602-038b omc 932723248
preface the h8/534 and h8/536 are high-performance single-chip hitachi-original microcomputers, featuring a high-speed cpu with 16-bit internal data paths and a full complement of on-chip supporting modules. they are ideal microcontrollers for a wide variety of medium-scale devices, including both office and industrial equipment and consumer products. the cpu has a general-register architecture. its instruction set is highly orthogonal and is optimized for fast execution of programs coded in the high-level c language. for further speed, the existing 10-mhz lineup has been extended to include high-speed versions that operate at 16 mhz. low-voltage versions that operate at 3 v and 2.7 v have also been developed. on-chip facilities include large ram and rom memories, numerous timers, serial i/o, an a/d converter, i/o ports, and other functions for compact implementation of high-performance application systems. h8/534 and h8/536 are available in both a ztat ? version* with on-chip prom, ideal for the early stages of production or for products with frequently-changing specifications, and a masked- rom version suitable for volume production. this manual gives a hardware description of the h8/534 and h8/536. for details of the instruction set, refer to the h8/500 series programming manual , which applies to all chips in the h8/500 series. * ztat (zero turn-around time) is a trademark of hitachi, ltd. 2
contents section 1 overview 1.1 features 1 1.2 block diagram ? 1.3 pin arrangements and functions ? 1.3.1 pin arrangement ? 1.3.2 pin functions 9 section 2 mcu operating modes and address space 2.1 overview 23 2.2 mode descriptions ?4 2.3 address space map 25 2.3.1 page segmentation 25 2.3.2 page 0 address allocations 26 2.4 mode control register (mdcr) ?7 section 3 cpu 3.1 overview 31 3.1.1 features ?1 3.1.2 address space ?2 3.1.3 register configuration 33 3.2 cpu register descriptions 34 3.2.1 general registers 34 3.2.2 control registers 35 3.2.3 initial register values ?0 3.3 data formats 41 3.3.1 data formats in general registers ?1 3.3.2 data formats in memory 42 3.4 instructions ?4 3.4.1 basic instruction formats ?4 3.4.2 addressing modes 45 3.4.3 effective address calculation 47 3.5 instruction set 50 3.5.1 overview ?0 3.5.2 data transfer instructions ?2 3.5.3 arithmetic instructions ?3 3.5.4 logic operations ?4 3.5.5 shift operations 55 3.5.6 bit manipulations 56 3.5.7 branching instructions 57
3.5.8 system control instructions 59 3.5.9 short-format instructions ?2 3.6 operating modes 62 3.6.1 minimum mode 62 3.6.2 maximum mode 63 3.7 basic operational timing 63 3.7.1 overview ?3 3.7.2 on-chip memory access cycle ?4 3.7.3 pin states during on-chip memory access ?5 3.7.4 register field access cycle (addresses h'fe80 to h'ffff) 66 3.7.5 pin states during register field access (addresses h'fe80 to h'ffff) 67 3.7.6 external access cycle 68 3.8 cpu states ?9 3.8.1 overview ?9 3.8.2 program execution state ?1 3.8.3 exception-handling state ?1 3.8.4 bus-released state 72 3.8.5 reset state ?7 3.8.6 power-down state 77 3.9 programming notes ?8 3.9.1 restriction on address location ?8 section 4 exception handling 4.1 overview 79 4.1.1 types of exception handling and their priority 79 4.1.2 hardware exception-handling sequence ?0 4.1.3 exception factors and vector table ?0 4.2 reset 83 4.2.1 overview ?3 4.2.2 reset sequence ?3 4.2.3 stack pointer initialization 84 4.3 address error ?7 4.3.1 illegal instruction prefetch 87 4.3.2 word data access at odd address ?7 4.3.3 off-chip address access in single-chip mode ?7 4.4 trace 88 4.5 interrupts 88 4.6 invalid instruction 91 4.7 trap instructions and zero divide ?1 4.8 cases in which exception handling is deferred ?1 4.8.1 instructions that disable interrupts ?1
4.8.2 disabling of exceptions immediately after a reset 92 4.8.3 disabling of interrupts after a data transfer cycle 92 4.9 stack status after completion of exception handling 93 4.9.1 pc value pushed on stack for trace, interrupts, trap instructions, and zero divide exceptions ?5 4.9.2 pc value pushed on stack for address error and invalid instruction exceptions 95 4.10 notes on use of the stack 95 section 5 interrupt controller 5.1 overview 97 5.1.1 features ?7 5.1.2 block diagram 98 5.1.3 register configuration 99 5.2 interrupt types ?9 5.2.1 external interrupts 99 5.2.2 internal interrupts 101 5.2.3 interrupt vector table ?02 5.3 register descriptions ?04 5.3.1 interrupt priority registers a to f (ipra to iprf) 104 5.3.2 timing of priority setting ?05 5.4 interrupt handling sequence ?05 5.4.1 interrupt handling flow ?05 5.4.2 stack status after interrupt handling sequence ?08 5.4.3 timing of interrupt exception-handling sequence 109 5.5 interrupts during operation of the data transfer controller 109 5.6 interrupt response time 112 section 6 data transfer controller 6.1 overview 113 6.1.1 features ?13 6.1.2 block diagram 113 6.1.3 register configuration 114 6.2 register descriptions ?15 6.2.1 data transfer mode register (dtmr) ?15 6.2.2 data transfer source address register (dtsr) 116 6.2.3 data transfer destination register (dtdr) ?16 6.2.4 data transfer count register (dtcr) ?16 6.2.5 data transfer enable registers a to f (dtea to dtef) 117 6.3 data transfer operation ?18 6.3.1 data transfer cycle 118
6.3.2 dtc vector table ?20 6.3.3 location of register information in memory ?22 6.3.4 length of data transfer cycle 122 6.4 procedure for using the dtc 124 6.5 example ?25 section 7 wait-state controller 7.1 overview 127 7.1.1 features ?27 7.1.2 block diagram 128 7.1.3 register configuration 128 7.2 wait-state control register ?29 7.3 operation in each wait mode 130 7.3.1 programmable wait mode 130 7.3.2 pin wait mode 131 7.3.3 pin auto-wait mode ?33 section 8 clock pulse generator 8.1 overview 135 8.1.1 block diagram 135 8.2 oscillator circuit 135 8.3 system clock divider 139 section 9 i/o ports 9.1 overview 141 9.2 port 1 144 9.2.1 overview ?44 9.2.2 port 1 registers ?44 9.2.3 pin functions in each mode ?47 9.3 port 2 150 9.3.1 overview ?50 9.3.2 port 2 registers ?51 9.3.3 pin functions in each mode ?52 9.4 port 3 153 9.4.1 overview ?53 9.4.2 port 3 registers ?54 9.4.3 pin functions in each mode ?55 9.5 port 4 156 9.5.1 overview ?56 9.5.2 port 4 registers ?57 9.5.3 pin functions in each mode ?58
9.6 port 5 159 9.6.1 overview ?59 9.6.2 port 5 registers ?60 9.6.3 pin functions in each mode ?61 9.6.4 built-in mos pull-up ?63 9.7 port 6 165 9.7.1 overview ?65 9.7.2 port 6 registers ?66 9.7.3 pin functions in each mode ?70 9.7.4 built-in mos pull-up ?72 9.8 port 7 173 9.8.1 overview ?73 9.8.2 port 7 registers ?73 9.8.3 pin functions 174 9.9 port 8 177 9.9.1 overview ?77 9.9.2 port 8 registers ?77 9.10 port 9 178 9.10.1 overview ?78 9.10.2 port 9 registers ?78 9.10.3 pin functions 179 section 10 16-bit free-running timers 10.1 overview 183 10.1.1 features ?83 10.1.2 block diagram 184 10.1.3 input and output pins ?85 10.1.4 register configuration 186 10.2 register descriptions ?87 10.2.1 free-running counter (frc)?'fe92, h'fea2, h'feb2 ?87 10.2.2 output compare registers a and b (ocra and ocrb)?'fe94 and h'fe96, h'fea4 and h'fea6, h'feb4 and h'feb6 188 10.2.3 input capture register (icr)?'fe98, h'fea8, h'feb8 ?88 10.2.4 timer control register (tcr) 189 10.2.5 timer control/status register (tcsr) ?91 10.3 cpu interface ?94 10.4 operation 196 10.4.1 frc incrementation timing ?96 10.4.2 output compare timing ?97 10.4.3 input capture timing 199 10.4.4 setting of frc overflow flag (ovf) 201
10.5 cpu interrupts and dtc interrupts ?01 10.6 synchronization of free-running timers 1 to 3 202 10.6.1 synchronization after a reset ?02 10.6.2 synchronization by writing to frcs 202 10.7 sample application 206 10.8 application notes 206 section 11 8-bit timer 11.1 overview 213 11.1.1 features ?13 11.1.2 block diagram 214 11.1.3 input and output pins ?15 11.1.4 register configuration 215 11.2 register descriptions ?15 11.2.1 timer counter (tcnt)?'fed4 215 11.2.2 time constant registers a and b (tcora and tcorb)?'fed2 and h'fed3 ?16 11.2.3 timer control register (tcr)?'fed0 ?16 11.2.4 timer control/status register (tcsr)?'fed1 218 11.3 operation 220 11.3.1 tcnt incrementation timing 220 11.3.2 compare match timing 221 11.3.3 external reset of tcnt ?23 11.3.4 setting of tcnt overflow flag ?24 11.4 cpu interrupts and dtc interrupts ?24 11.5 sample application 225 11.6 application notes 226 section 12 pwm timer 12.1 overview 233 12.1.1 features ?33 12.1.2 block diagram 233 12.1.3 input and output pins ?34 12.1.4 register configuration 235 12.2 register descriptions ?35 12.2.1 timer counter (tcnt)?'fec2, h'fec4, h'feca ?35 12.2.2 duty register (dtr)?'fec1, h'fec5, h'fec9 236 12.2.3 timer control register (tcr)?'fec0, h'fec4, h'fec8 ?36 12.3 operation 238 12.4 application notes 240
section 13 watchdog timer 13.1 overview 241 13.1.1 features ?41 13.1.2 block diagram 242 13.1.3 register configuration 242 13.2 register descriptions ?43 13.2.1 timer counter tcnt?'feec (write), h'feed (read) 243 13.2.2 timer control/status register (tcsr)?'feec ?43 13.2.3 reset control/status register (rstcsr)?'ff14 (write), h'ff15 (read) 245 13.2.4 notes on register access 246 13.3 operation 248 13.3.1 watchdog timer mode ?48 13.3.2 interval timer mode ?49 13.3.3 operation in software standby mode ?50 13.3.4 setting of overflow flag 250 13.3.5 setting of watchdog timer reset (wrst) bit ?51 13.4 application notes 252 section 14 serial communication interface 14.1 overview 255 14.1.1 features ?55 14.1.2 block diagram 256 14.1.3 input and output pins ?57 14.1.4 register configuration 257 14.2 register descriptions ?58 14.2.1 receive shift register (rsr) ?58 14.2.2 receive data register (rdr)?'fedd, h'fef5 258 14.2.3 transmit shift register (tsr) 258 14.2.4 transmit data register (tdr)?'fedb, h'fef3 ?59 14.2.5 serial mode register (smr)?'fed8, h'fef0 ?59 14.2.6 serial control register (scr)?'feda, h'fef2 261 14.2.7 serial status register (ssr)?'fedc, h'fef4 ?63 14.2.8 bit rate register (brr)?'fed9, h'fef1 265 14.3 operation 270 14.3.1 overview ?70 14.3.2 asynchronous mode ?71 14.3.3 synchronous mode ?75 14.4 cpu interrupts and dtc interrupts ?79 14.5 application notes 280
section 15 a/d converter 15.1 overview 283 15.1.1 features ?83 15.1.2 block diagram 284 15.1.3 input pins 285 15.1.4 register configuration 285 15.2 register descriptions ?86 15.2.1 a/d data registers (addr)?'fee0 to h'fee7 286 15.2.2 a/d control/status register (adcsr)?'fee8 ?87 15.2.3 a/d control register (adcr)?'fee9 ?89 15.3 cpu interface ?90 15.4 operation 291 15.4.1 single mode (scan = 0) ?91 15.4.2 scan mode (scan = 1) 294 15.4.3 input sampling time and a/d conversion time ?96 15.4.4 external triggering of a/d conversion ?97 15.5 interrupts and the data transfer controller ?98 section 16 ram 16.1 overview 299 16.1.1 block diagram 299 16.1.2 register configuration 300 16.2 ram control register (ramcr) ?00 16.3 operation 300 16.3.1 expanded modes (modes 1, 2, 3, and 4) 300 16.3.2 single-chip mode (mode 7) ?01 section 17 rom 17.1 overview 303 17.1.1 block diagram 303 17.2 prom mode 304 17.2.1 prom mode setup ?04 17.2.2 socket adapter pin arrangements and memory map 305 17.3 h8/534 programming ?08 17.3.1 writing and verifying ?08 17.3.2 notes on writing ?11 17.4 h8/536 programming ?12 17.4.1 writing and verifying ?12 17.4.2 notes on programming ?15 17.5 reliability of written data ?17 17.6 erasing of data ?18
17.7 handling of windowed packages 319 section 18 power-down state 18.1 overview 321 18.2 sleep mode 322 18.2.1 transition to sleep mode 322 18.2.2 exit from sleep mode ?22 18.3 software standby mode ?22 18.3.1 transition to software standby mode 322 18.3.2 software standby control register (sbycr) 323 18.3.3 exit from software standby mode ?24 18.3.4 sample application of software standby mode 324 18.3.5 application notes ?25 18.4 hardware standby mode ?25 18.4.1 transition to hardware standby mode ?25 18.4.2 recovery from hardware standby mode ?26 18.4.3 timing sequence of hardware standby mode ?26 section 19 e clock interface 19.1 overview 327 section 20 electrical specifications 20.1 absolute maximum ratings 331 20.2 electrical characteristics 331 20.2.1 dc characteristics 331 20.2.2 ac characteristics 340 20.2.3 a/d converter characteristics 349 20.3 mcu operational timing 350 20.3.1 bus timing 351 20.3.2 control signal timing 354 20.3.3 clock timing 355 20.3.4 i/o port timing ?57 20.3.5 16-bit free-running timer timing 358 20.3.6 8-bit timer timing ?59 20.3.7 pulse width modulation timer timing 360 20.3.8 serial communication interface timing ?60 20.3.9 a/d trigger signal input timing ?61 appendix a instructions a.1 instruction set 363 a.2 instruction codes ?68
a.3 operation code map 379 a.4 instruction execution cycles ?84 a.4.1 calculation of instruction execution states 384 a.4.2 tables of instruction execution cycles 385 appendix b register field b.1 register addresses and bit names 393 b.2 register descriptions ?98 appendix c i/o port schematic diagrams c.1 schematic diagram of port 1 ?37 c.2 schematic diagram of port 2 ?44 c.3 schematic diagram of port 3 ?45 c.4 schematic diagram of port 4 ?46 c.5 schematic diagram of port 5 ?47 c.6 schematic diagram of port 6 ?48 c.7 schematic diagram of port 7 ?50 c.8 schematic diagram of port 8 ?55 c.9 schematic diagram of port 9 ?56 appendix d memory maps ?63 appendix e pin states e.1 port state of each pin state ?65 e.2 pin states in reset state ?68 appendix f timing of transition to and recovery from hardware standby mode 475 appendix g package dimensions 476
figures 1-1 block diagram ? 1-2 pin arrangement (cp-84, top view) 6 1-3 pin arrangement (cg-84, top view) 7 1-4 pin arrangement (fp-80a, tfp-80c, top view) ? 2-1 h8/534 memory map in each operating mode 28 2-2 h8/536 memory map in each operating mode 29 3-1 cpu operating modes ?2 3-2 registers in the cpu 33 3-3 stack pointer 34 3-4 combinations of page registers with other registers 38 3-5 short absolute addressing mode and base register 39 3-6 on-chip memory access timing 64 3-7 pin states during access to on-chip memory 65 3-8 register field access timing 66 3-9 pin states during register field access 67 3-10 (a) external access cycle (read access) ?8 3-10 (b) external access cycle (write access) 69 3-11 operating states ?0 3-12 state transitions 71 3-13 bus-right release cycle (during on-chip memory access cycle) ?3 3-14 bus-right release cycle (during external access cycle) ?4 3-15 bus-right release cycle (during internal cpu operation) ?5 4-1 types of factors causing exception handling ?1 4-2 reset vector ?4 4-3 reset sequence (minimum mode, on-chip memory) ?5 4-4 reset sequence (maximum mode, external memory) ?6 4-5 interrupt sources (and number of interrupt types) 90 5-1 interrupt controller block diagram 98 5-2 interrupt handling flowchart 107 5-3 (a) stack before and after interrupt exception-handling (minimum mode) 108 5-3 (b) stack before and after interrupt exception-handling (maximum mode) ?09 5-4 interrupt sequence (minimum mode, on-chip memory) 110 5-5 interrupt sequence (maximum mode, external memory) 111 6-1 block diagram of data transfer controller 114 6-2 flowchart of data transfer cycle 119 6-3 dtc vector table 120 6-4 dtc vector table entry 121 6-5 order of register information ?22 6-6 use of dtc to receive data via serial communication interface 1 126 7-1 block diagram of wait-state controller ?28
7-2 programmable wait mode ?31 7-3 pin wait mode ?32 7-4 pin auto-wait mode 133 8-1 block diagram of clock pulse generator ?35 8-2 connection of crystal oscillator (example) ?36 8-3 crystal oscillator equivalent circuit ?36 8-4 notes on board design around external crystal ?37 8-5 external clock input (example) 137 8-6 external clock input (examples) 138 8-7 phase relationship of ?clock and e clock ?39 9-1 pin functions of port 1 144 9-2 pin functions of port 2 150 9-3 port 2 pin functions in expanded modes 152 9-4 port 2 pin functions in single-chip mode 153 9-5 pin functions of port 3 153 9-6 port 3 pin functions in expanded modes 155 9-7 port 3 pin functions in single-chip mode 156 9-8 pin functions of port 4 156 9-9 port 4 pin functions in expanded modes 158 9-10 port 4 pin functions in single-chip mode 159 9-11 pin functions of port 5 159 9-12 port 5 pin functions in modes 1 and 3 161 9-13 port 5 pin functions in modes 2 and 4 162 9-14 port 5 pin functions in single-chip mode 162 9-15 pin functions of port 6 166 9-16 port 6 pin functions in mode 3 ?70 9-17 port 6 pin functions in mode 4 ?70 9-18 port 6 pin functions in modes 7, 2, and 1 ?71 9-19 pin functions of port 7 173 9-20 pin functions of port 8 177 9-21 pin functions of port 9 178 10-1 block diagram of 16-bit free-running timer ?84 10-2 (a) write access to frc (when cpu writes h'aa55) ?95 10-2 (b) read access to frc (when frc contains h'aa55) ?96 10-3 increment timing for external clock input 197 10-4 setting of output compare flags 198 10-5 timing of output compare a 198 10-6 clearing of frc by compare-match a ?99 10-7 input capture timing (usual case) ?99 10-8 input capture timing (1-state delay) ?00 10-9 setting of input capture flag 200
10-10 setting of overflow flag (ovf) 201 10-11 square-wave output (example) 206 10-12 frc write-clear contention ?07 10-13 frc write-increment contention ?08 10-14 contention between ocr write and compare-match 209 11-1 block diagram of 8-bit timer ?14 11-2 count timing for external clock input ?21 11-3 setting of compare-match flags ?22 11-4 timing of timer output ?22 11-5 timing of compare-match clear 223 11-6 timing of external reset ?23 11-7 setting of overflow flag (ovf) 224 11-8 example of pulse output ?25 11-9 tcnt write-clear contention 226 11-10 tcnt write-increment contention ?27 11-11 contention between tcor write and compare-match 228 12-1 block diagram of pwm timer ?34 12-2 pwm timing ?39 13-1 block diagram of timer counter 242 13-2 writing to tcnt and tcsr 247 13-3 writing to rstcsr ?47 13-4 operation in watchdog timer mode ?49 13-5 operation in interval timer mode ?49 13-6 setting of ovf bit ?50 13-7 setting of wrst bit and internal reset signal 251 13-8 tcnt write-increment contention ?52 13-9 reset circuit (example) 253 14-1 block diagram of serial communication interface 256 14-2 data format in asynchronous mode ?71 14-3 phase relationship between clock output and transmit data ?72 14-4 data format in synchronous mode ?76 14-5 sampling timing (asynchronous mode) 282 15-1 block diagram of a/d converter 284 15-2 read access to a/d data register (when register contains h'aa40) ?90 15-3 a/d operation in single mode (when channel 1 is selected) ?93 15-4 a/d operation in scan mode (when channels 0 to 2 are selected) ?95 15-5 a/d conversion timing 296 15-6 timing of setting of adst bit ?97 16-1 block diagram of on-chip ram ?99 17-1 block diagram of on-chip rom ?04 17-2 (a) socket adapter pin arrangements (h8/534) ?06
17-2 (b) socket adapter pin arrangements (h8/536) ?07 17-3 memory map in prom mode 308 17-4 high-speed programming flowchart (h8/534) 309 17-5 prom write/verify timing (h8/534) ?11 17-6 high-speed programming flowchart (h8/536) 313 17-7 prom write/verify timing (h8/536) ?15 17-8 recommended screening procedure ?17 18-1 nmi timing of software standby mode (application example) ?25 18-2 hardware standby sequence ?26 19-1 execution cycle of instruction synchronized with e clock in expanded modes (maximum synchronization delay) 328 19-2 execution cycle of instruction synchronized with e clock in expanded modes (minimum synchronization delay) ?29 20-1 example of circuit for driving a darlington transistor pair 339 20-2 example of circuit for driving an led 339 20-3 output load circuit ?47 20-4 basic bus cycle (without wait states) in expanded modes ?51 20-5 basic bus cycle (with 1 wait state) in expanded modes ?52 20-6 bus cycle synchronized with e clock 353 20-7 reset input timing 354 20-8 reset output timing 354 20-9 interrupt input timing ?54 20-10 bus release state timing 355 20-11 e clock timing 355 20-12 clock oscillator stabilization timing ?56 20-13 i/o port input/output timing 357 20-14 free-running timer input/output timing 358 20-15 external clock input timing for free-running timers 358 20-16 8-bit timer output timing 359 20-17 8-bit timer clock input timing 359 20-18 8-bit timer reset input timing 359 20-19 pwm timer output timing 360 20-20 sci input clock timing 360 20-21 sci input/output timing (synchronous mode) 360 20-22 a/d trigger signal input timing 361 c-1 (a) schematic diagram of port 1, pin p1 0 437 c-1 (b) schematic diagram of port 1, pin p1 1 437 c-1 (c) schematic diagram of port 1, pin p1 2 ?38 c-1 (d) schematic diagram of port 1, pin p1 3 439 c-1 (e) schematic diagram of port 1, pin p1 4 ?40 c-1 (f) schematic diagram of port 1, pin p1 5 441
c-1 (g) schematic diagram of port 1, pin p1 6 442 c-1 (h) schematic diagram of port 1, pin p1 7 443 c-2 schematic diagram of port 2 ?44 c-3 schematic diagram of port 3 ?45 c-4 schematic diagram of port 4 ?46 c-5 schematic diagram of port 5 ?47 c-6 (a) schematic diagram of port 6, pin p6 0 448 c-6 (b) schematic diagram of port 6, pin p6 1 to p6 3 449 c-7 (a) schematic diagram of port 7, pin p7 0 450 c-7 (b) schematic diagram of port 7, pins p7 1 and p7 2 ?51 c-7 (c) schematic diagram of port 7, pin p7 3 452 c-7 (d) schematic diagram of port 7, pins p7 4 , p7 5 and p7 6 453 c-7 (e) schematic diagram of port 7, pin p7 7 454 c-8 schematic diagram of port 8 ?55 c-9 (a) schematic diagram of port 9, pins p9 0 and p9 1 ?56 c-9 (b) schematic diagram of port 9, pin p9 2 457 c-9 (c) schematic diagram of port 9, pin p9 3 458 c-9 (d) schematic diagram of port 9, pin p9 4 459 c-9 (e) schematic diagram of port 9, pin p9 5 460 c-9 (f) schematic diagram of port 9, pin p9 6 461 c-9 (g) schematic diagram of port 9, pin p9 7 462 e-1 reset during memory access (mode 1) 469 e-2 reset during memory access (mode 2) 470 e-3 reset during memory access (mode 3) 472 e-4 reset during memory access (mode 4) 473 e-5 reset during memory access (mode 7) 474 g-1 package dimensions (cp-84) 476 g-2 package dimensions (cg-84) ?76 g-3 package dimensions (fp-80a) 477 g-4 package dimensions (tfp-80c) ?77 tables 1-1 features 2 1-2 pin arrangements in each operating mode (cp-84, cg-84) ? 1-3 pin arrangements in each operating mode (fp-80a, tfp-80c) ?3 1-4 pin functions ?7 2-1 operating modes ?3 2-2 mode control register 27 3-1 interrupt mask levels 36 3-2 interrupt mask bits after an interrupt is accepted 36 3-3 initial values of registers 41
3-4 general register data formats 42 3-5 data formats in memory ?3 3-6 data formats on the stack ?4 3-7 addressing modes ?6 3-8 effective address calculation ?7 3-9 instruction classification ?0 3-10 data transfer instructions ?2 3-11 arithmetic instructions 53 3-12 logic operation instructions ?4 3-13 shift instructions 55 3-14 bit-manipulation instructions 56 3-15 branching instructions ?7 3-16 system control instructions 59 3-17 short-format instructions and equivalent general formats ?2 4-1 (a) exceptions and their priority 79 4-1 (b) instruction exceptions ?9 4-2 exception vector table 82 4-3 stack after exception handling sequence ?3 5-1 interrupt controller registers 99 5-2 interrupts, vectors, and priorities 103 5-3 assignment of interrupt priority registers 104 5-4 number of states before interrupt service 112 6-1 internal control registers of the dtc ?14 6-2 data transfer enable registers 115 6-3 assignment of data transfer enable registers ?17 6-4 addresses of dtc vectors ?21 6-5 number of states per data transfer 123 6-6 number of states before interrupt service 124 6-7 dtc control register information set in ram ?25 7-1 register configuration ?28 7-2 wait modes 130 8-1 (1) external crystal parameters (hd6475368r, hd6475348r, hd6435368r, hd6435348r) ?36 8-1 (2) external crystal parameters (hd6475368s, hd6475348s, hd6435368s, hd6435348s) ?36 9-1 input/output port summary 142 9-2 port 1 registers 144 9-3 port 1 pin functions in expanded modes 147 9-4 port 1 pin functions in single-chip modes 149 9-5 port 2 registers 151 9-6 port 3 registers 154
9-7 port 4 registers 157 9-8 port 5 registers 160 9-9 status of mos pull-ups for port 5 163 9-10 port 6 registers 166 9-11 port 6 pin functions in modes 7, 2, and 1 ?71 9-12 status of mos pull-ups for port 5 172 9-13 port 7 registers 173 9-14 port 7 pin functions ?75 9-15 port 8 registers 177 9-16 port 9 registers 178 9-17 port 9 pin functions ?80 10-1 input and output pins of free-running timer module 185 10-2 register configuration ?86 10-3 free-running timer interrupts 201 10-4 synchronization by writing to frcs ?02 10-5 effect of changing internal clock sources ?10 11-1 input and output pins of 8-bit timer 215 11-2 8-bit timer registers ?15 11-3 8-bit timer interrupts 224 11-4 priority order of timer output 229 11-5 effect of changing internal clock sources ?29 12-1 output pins of pwm timer module ?34 12-2 pwm timer registers ?35 12-3 pwm timer parameters for 10 mhz system clock ?38 13-1 register configuration ?42 13-2 read addresses of tcnt and tcsr 248 14-1 sci input/output pins 257 14-2 sci registers ?57 14-3 examples of brr settings in asynchronous mode?65 14-4 examples of brr settings in synchronous mode 269 14-5 communication formats used by sci 270 14-6 sci clock source selection ?70 14-7 data formats in asynchronous mode ?72 14-8 receive errors ?75 14-9 sci interrupts ?80 14-10 ssr bit states and data transfer when multiple receive errors occur ?81 15-1 a/d input pins ?85 15-2 a/d registers ?85 15-3 assignment of data registers to analog input channels ?86 15-4 a/d conversion time (single mode) ?97 16-1 ram control register ?00
17-1 rom usage in each mcu mode 303 17-2 selection of prom mode ?04 17-3 socket adapter ?05 17-4 selection of sub-modes in prom mode (h8/534) 308 17-5 dc characteristics (h8/534) (when v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, v ss = 0 v, ta = 25?c 5?c) 310 17-6 ac characteristics (h8/534) (when v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, ta = 25?c 5?c) 310 17-7 selection of sub-modes in prom mode (h8/536) 312 17-8 dc characteristics (h8/536) (when v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, v ss = 0 v, ta = 25?c 5?c) 314 17-9 ac characteristics (h8/536) (when v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, ta = 25?c 5?c) 314 17-10 prom writers ?16 17-11 erasing conditions ?18 17-12 socket for 84-pin lcc package 319 18-1 power-down state ?21 18-2 software standby control register ?23 20-1 absolute maximum ratings 331 20-2 dc characteristics (5-v versions) ?32 20-3 dc characteristics (3-v s-mask versions)334 20-4 dc characteristics (2.7-v s-mask versions)?36 20-5 allowable output current values (5-v versions) 338 20-6 allowable output current values (3-v s-mask versions)?38 20-7 allowable output current values (2.7-v s-mask versions)339 20-8 (1) bus timing (r-mask versions) 340 20-8 (2) bus timing (s-mask versions)?42 20-9 (1) control signal timing (r-mask versions)?44 20-9 (2) control signal timing (s-mask versions) ?45 20-10 timing conditions of on-chip supporting modules ?46 20-11 a/d converter characteristics (5-v versions) ?49 20-12 a/d converter characteristics350 a-1 (a) machine language coding [general format] ?72 a-1 (b) machine language coding [special format: short format] 376 a-1 (c) machine language coding [special format: branch instruction] 377 a-1 (d) machine language coding [special format: system control instructions] ?78 a-2 operation codes in byte 1 ?79 a-3 operation codes in byte 2 (axxx) 380 a-4 operation codes in byte 2 (05xx, 15xx, 0dxx, 1dxx, bxxx, cxxx, dxxx, exxx, fxxx) ?81 a-5 operation codes in byte 2 (04xx, 0cxx) 382
a-6 operation codes in bytes 2 and 3 (11xx, 01xx, 06xx, 07xx, xx00xx) 383 a-7 instruction execution cycles (1) ?87 a-7 instruction execution cycles (2) 388 a-7 instruction execution cycles (3) 389 a-7 instruction execution cycles (4) 390 a-7 instruction execution cycles (5) 391 a-7 instruction execution cycles (6) 392 a-8 (a) adjusted value (branch instruction) ?92 a-8 (b) adjusted value (other instructions by addressing modes) 392 c-1 (a) port 1 port read (pin p1 0 ) ?37 c-1 (b) port 1 port read (pin p1 1 ) ?38 c-1 (c) port 1 port read (pin p1 2 ) ?38 c-1 (d) port 1 port read (pin p1 3 ) ?39 c-1 (e) port 1 port read (pin p1 4 ) ?40 c-1 (f) port 1 port read (pin p1 5 ) ?41 c-1 (g) port 1 port read (pin p1 6 ) ?42 c-1 (h) port 1 port read (pin p1 7 ) ?43 c-2 port 2 port read ?44 c-3 port 3 port read ?45 c-4 port 4 port read ?46 c-5 port 5 port read ?47 c-6 (a) port 6 port read (pin p6 0 ) ?48 c-6 (b) port 6 port read (pin p6 1 to p6 3 ) 449 c-7 (a) port 7 port read (pin p7 0 ) ?50 c-7 (b) port 7 port read (pins p7 1 , p7 2 ) 451 c-7 (c) port 7 port read (pin p7 3 ) ?52 c-7 (d) port 7 port read (pins p7 4 to p7 6 ) 453 c-7 (e) port 7 port read (pin p7 7 ) ?54 c-9 (a) port 9 port read (pins p9 0 , p9 1 ) 456 c-9 (b) port 9 port read (pin p9 2 ) ?57 c-9 (c) port 9 port read (pin p9 3 ) ?58 c-9 (d) port 9 port read (pin p9 4 ) ?59 c-9 (e) port 9 port read (pin p9 5 ) ?60 c-9 (f) port 9 port read (pin p9 6 ) ?61 c-9 (g) port 9 port read (pin p9 7 ) ?62 d-1 h8/534 memory map 463 d-2 h8/536 memory map 464 e-1 port state 465 e-2 mos pull-up state 467
section 1 overview 1.1 features the h8/534 and h8/536 are cmos microcomputer units (mcus) comprising a cpu core plus a full range of supporting functions?n entire system integrated onto a single chip. the cpu features a highly orthogonal instruction set that permits addressing modes and data sizes to be specified independently in each instruction. an internal 16-bit architecture and 16-bit access to on-chip memory enhance the cpus data-processing capability and provide the speed needed for realtime control applications. the on-chip supporting functions include ram, rom, timers, a serial communication interface (sci), a/d conversion, and i/o ports. an on-chip data transfer controller (dtc) can transfer data in either direction between memory and i/o independently of the cpu. for the on-chip rom, a choice is offered between masked rom and programmable rom (prom). the prom version can be programmed by the user with a general-purpose prom writer. table 1-1 lists the main features of the h8/534 and h8/536. 1
table 1-1 features feature description cpu general-register machine ? eight 16-bit general registers ? five 8-bit and two 16-bit control registers high speed ? maximum clock rate: 10 mhz (oscillator frequency: 20 mhz, r-mask versions) 16 mhz (oscillator frequency: 32 mhz, s-mask versions) expanded operating modes supporting external memory ? minimum mode: up to 64-kbyte address space ? maximum mode: up to 1 m-byte address space highly orthogonal instruction set ? addressing modes and data size can be specified independently for each instruction 1.5 addressing modes ? register-register operations ? register-memory operations instruction set optimized for c language ? special short formats for frequently-used instructions and addressing modes memory ? 2-kbyte high-speed ram on-chip (h8/534) ? 32-kbyte programmable or masked rom on-chip memory ? 2-kbyte high-speed ram on-chip (h8/536) ? 62-kbyte programmable or masked rom on-chip 16-bit free- each channel provides: running ? 1 free-running counter (which can count external events) timer (frt) ? 2 output-compare registers (3 channels) ? 1 input capture register 8-bit timer ? one 8-bit up-counter (which can count external events) (1 channel) ? 2 time constant registers pwm timer ? generates pulses with any duty ratio from 0 to 100% (3 channels) ? resolution: 1/250 watchdog ? an overflow generates a nonmaskable interrupt timer (wdt) ? can also be used as an interval timer (1 channel) 2
table 1-1 features (cont) feature description serial com- asynchronous or synchronous mode (selectable) munication full duplex: can send and receive simultaneously interface (sci) built-in baud rate generator (2 channels) a/d converter 10-bit resolution 8 channels, controllable in single mode or scan mode (selectable) sample-and-hold function start of a/d conversion can be externally triggered i/o ports 57 input/output pins (six 8-bit ports, one 5-bit port, one 4-bit port) 8 input-only pins (one 8-bit port) interrupt 7 external interrupt pins (nmi, irq0, irq1 to irq5) controller 23 internal interrupts (intc) 8 priority levels data transfer performs bidirectional data transfer between memory and i/o independently controller (dtc) of the cpu wait-state can insert wait states in access to external memory or i/o controller (wsc) operating 5 mcu operating modes modes expanded minimum modes, supporting up to 64 kbytes external memory with or without using on-chip rom (modes 1 and 2) expanded maximum modes, supporting up to 1 mbyte external memory with or without using on-chip rom (modes 3 and 4) single-chip mode (mode 7) 3 power-down modes sleep mode software standby mode hardware standby mode other features e clock output available clock generator on-chip model name package options rom hd6475348rcg 84-pin windowed lcc (cg-84) prom hd6475348rcp 84-pin plcc (cp-84) hd6475348rf 80-pin qfp (fp-80a) hd6435348rcp 84-pin plcc (cp-84) mask hd6435348rf 80-pin qfp (fp-80a) rom model name package options rom hd6475348scg 84-pin windowed lcc (cg-84) prom hd6475348scp 84-pin plcc (cp-84) hd6475348sf 80-pin qfp (fp-80a) hd6475348stf 80-pin tqfp (tfp-80c) hd6435348scp 84-pin plcc (cp-84) mask hd6435348sf 80-pin qfp (fp-80a) rom hd6435348stf 80-pin tqfp (tfp-80c) product line-up (h8/534 r-mask versions) product line-up (h8/534 s-mask versions) 3
table 1-1 features (cont) feature description model name package options rom hd6475368rcg 84-pin windowed lcc (cg-84) prom hd6475368rcp 84-pin plcc (cp-84) hd6475368rf 80-pin qfp (fp-80a) hd6435368rcp 84-pin plcc (cp-84) mask hd6435368rf 80-pin qfp (fp-80a) rom model name package options rom hd6475368scg 84-pin windowed lcc (cg-84) prom hd6475368scp 84-pin plcc (cp-84) hd6475368sf 80-pin qfp (fp-80a) hd6475368stf 80-pin tqfp (tfp-80c) hd6435368scp 84-pin plcc (cp-84) mask hd6435368sf 80-pin qfp (fp-80a) rom hd6435368stf 80-pin tqfp (tfp-80c) product 16-mhz high- 3-v 2.7-v line-up regular speed low-voltage low-voltage versions versions versions * versions * model prom hd6475368r hd6475368s hd6475368sv hd6475368sv name hd6475348r hd6475348s hd6475348sv hd6475348sv mask hd6435368r hd6435368s hd6435368sv hd6435368sv rom hd6435348r hd6435348s HD6435348SV HD6435348SV clock speed 0.5 mhz to 2 mhz to 2 mhz to 2 mhz to supply voltage 10 mhz 16 mhz 10 mhz 8 mhz 5 v 10% 5 v 10% 3 v to 5.5 v 2.7 v to 5.5 v notes : the product codes of the 3-v and 2.7-v low-voltage versions include a suffix that identifies the clock speed. examples are shown below for the h8/536 prom version in an 80-pin qfp package. examples: 3-v versions: hd6475368svf10 2.7-v versions: hd6475368svf8 * under development product line-up (h8/536 r-mask versions) product line-up (h8/536 s-mask versions) 4
1.2 block diagram figure 1-1 shows a block diagram of the h8/534 and h8/536. cpu p4 /a 7 7 p4 /a 6 6 p4 /a 5 5 p4 /a 4 4 p4 /a 3 3 p4 /a 2 2 p4 /a 1 1 p4 /a 0 0 p5 /a 15 7 p5 /a 14 6 p5 /a 13 5 p5 /a 12 4 p5 /a 11 3 p5 /a 10 2 p5 /a 9 1 p5 /a 8 0 p7 /ftoa 1 7 p7 /fti 2 2 p7 /fti 1 1 p7 /tmci 0 p7 /ftob /ftci 3 6 3 p7 /ftob /ftci 2 5 2 p7 /ftob /ftci 1 4 p7 /fti /tmri 3 3 1 p8 /an 7 7 p8 /an 6 6 p8 /an 5 5 p8 /an 4 4 p8 /an 3 3 p8 /an 2 2 p8 /an 1 1 p8 /an 0 0 8-bit timer 16-bit free running timer (x 3 channels) watchdog timer serial communication interface pwm timer (x 3 channels) 10-bit a/d converter port 9 port 8 port 7 port 6 port 5 port 4 port 3 port 2 port 1 clock gener- ator extal xtal wait- state controller ram 2 kbyte prom/mask rom 32 kbytes (h8/534) 62 kbytes (h8/536) interrupt controller data transfer controller v cc v cc v ss v ss v ss v ss v ss v ss * av cc av ss nmi res stby md 0 md 1 md 2 * cp-84 and cg-84 only p3 /d 7 7 p3 /d 6 6 p3 /d 5 5 p3 /d 4 4 p3 /d 3 3 p3 /d 2 2 p3 /d 1 1 p3 /d 0 0 p2 /wr 4 p2 /rd 3 p2 /ds 2 p2 /r/w 1 p2 /as 0 data bus (low) data bus (high) address bus p1 /tmo 7 p1 /irq /adtrg 1 6 p1 /irq 0 5 p1 /wait 4 p1 /breq 3 p1 /back 2 p1 /e 1 p1 / 0 p6 /pw /irq /a 3 3 5 19 p6 /pw /irq /a 2 2 4 18 p6 /pw /irq /a 1 1 3 17 p6 /irq /a 2 0 16 p9 /sck 7 p9 /rxd 6 p9 /txd 5 p9 /sck /pw 3 2 p9 /rxd /pw 2 2 p9 /txd /pw 1 2 p9 /ftoa 3 1 p9 /ftoa 2 0 1 1 1 4 3 2 5 figure 1-1 block diagram
1.3 pin arrangements and functions 1.3.1 pin arrangement figure 1-2 shows the pin arrangement of the cp-84 package. figure 1-3 shows the pin arrangement of the cg-84 package. figure 1-4 shows the pin arrangement of the fp-80a package. these pin arrangements apply to both the h8/534 and h8/536. p2 /r/w p2 /ds p2 /rd p2 /wr v md md md stby res nmi nc v p3 /d p3 /d p3 /d p3 /d p3 /d p3 /d p3 /d p3 /d 1 2 3 4 cc 0 1 2 ss 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 plcc-84 1 pin h8/534 hd6475348cp japan av p8 /an p8 /an p8 /an p8 /an p8 /an p8 /an p8 /an p8 /an av v p7 /ftoa p7 /ftob /ftci p7 /ftob /ftci p7 /ftob /ftci p7 /fti /tmri p7 /fti p7 /fti p7 /tmci v p6 /pw /irq /a cc 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 ss ss 7 6 5 4 3 2 1 0 cc 3 1 3 2 1 3 2 1 3 2 1 19 3 5 p4 /a p4 /a p4 /a p4 /a p4 /a p4 /a p4 /a p4 /a v v p5 /a p5 /a p5 /a p5 /a p5 /a p5 /a p5 /a p5 /a p6 /irq /a p6 /pw /irq /a p6 /pw /irq /a 0 1 2 3 4 5 6 7 ss ss 0 8 1 9 2 10 3 11 4 12 5 13 6 14 7 15 2 16 1 17 2 18 0 1 2 3 4 5 6 7 0 1 2 3 4 1 pin h8/536 hd6475368cp japan p2 /as p1 /tmo p1 /irq /adtrg p1 /irq p1 /wait p1 /breq p1 /back p1 /e p1 / v xtal extal v p9 /sck p9 /rxd p9 /txd p9 /sck /pw p9 /rxd /pw p9 /txd /pw p9 /ftoa p9 /ftoa 0 7 6 5 4 3 2 1 0 ss ss 7 6 5 4 3 2 1 0 2 2 2 3 2 1 0 3 2 1 1 1 1 6 figure 1-2 pin arrangement (cp-84, top view)
lcc-84 p2 /r/w p2 /ds p2 /rd p2 /wr v md md md stby res nmi nc v p3 /d p3 /d p3 /d p3 /d p3 /d p3 /d p3 /d p3 /d 1 2 3 4 cc 0 1 2 ss 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 index h8/534 hd6475348cg japan index h8/536 hd6475368cg japan p2 /as p1 /tmo p1 /irq /adtrg p1 /irq p1 /wait p1 /breq p1 /back p1 /e p1 / v xtal extal v p9 /sck p9 /rxd p9 /txd p9 /sck /pw p9 /rxd /pw p9 /txd /pw p9 /ftoa p9 /ftoa 0 7 6 5 4 3 2 1 0 ss ss 7 6 5 4 3 2 1 0 3 2 1 3 2 1 0 1 1 1 2 2 2 av p8 /an p8 /an p8 /an p8 /an p8 /an p8 /an p8 /an p8 /an av v p7 /ftoa p7 /ftob /ftci p7 /ftob /ftci p7 /ftob /ftci p7 /fti /tmri p7 /fti p7 /fti p7 /tmci v p6 /pw /irq /a cc 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 ss ss 7 6 5 4 3 2 1 0 cc 3 1 3 2 1 3 2 1 3 2 1 19 5 3 p4 /a p4 /a p4 /a p4 /a p4 /a p4 /a p4 /a p4 /a v v p5 /a p5 /a p5 /a p5 /a p5 /a p5 /a p5 /a p5 /a p6 /irq /a p6 /pw /irq /a p6 /pw /irq /a 0 1 2 3 4 5 6 7 ss ss 0 8 1 9 2 10 3 11 4 12 5 13 6 14 7 15 2 16 3 17 4 18 0 1 2 3 4 5 6 7 0 1 2 1 2 figure 1-3 pin arrangement (cg-84, top view) 7
p2 /r/w p2 /ds p2 /rd p2 /wr v md md md stby res nmi v p3 /d p3 /d p3 /d p3 /d p3 /d p3 /d p3 /d p3 /d 1 2 3 4 cc 0 1 2 ss 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 qfp-80a tqfp-80c h8/534 hd6475348f japan pin 1 h8/536 hd6475368f japan pin 1 p2 /as p1 /tmo p1 /irq /adtrg p1 /irq p1 /wait p1 /breq p1 /back p1 /e p1 / v xtal extal p9 /sck p9 /rxd p9 /txd p9 /sck /pw p9 /rxd /pw p9 /txd /pw p9 /ftoa p9 /ftoa 0 7 6 5 4 3 2 1 0 ss 7 6 5 4 3 2 1 0 3 2 1 3 2 1 0 1 1 1 2 2 2 av p8 /an p8 /an p8 /an p8 /an p8 /an p8 /an p8 /an p8 /an av p7 /ftoa p7 /ftob /ftci p7 /ftob /ftci p7 /ftob /ftci p7 /fti /tmri p7 /fti p7 /fti p7 /tmci v p6 /pw /irq /a cc 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 ss 7 6 5 4 3 2 1 0 cc 3 1 3 2 1 3 2 1 3 2 1 3 19 5 p4 /a p4 /a p4 /a p4 /a p4 /a p4 /a p4 /a p4 /a v p5 /a p5 /a p5 /a p5 /a p5 /a p5 /a p5 /a p5 /a p6 /irq /a p6 /pw /irq /a p6 /pw /irq /a 0 1 2 3 4 5 6 7 ss 0 8 1 9 2 10 3 11 4 12 5 13 6 14 7 15 2 16 3 17 4 18 0 1 2 3 4 5 6 7 1 2 0 1 2 qfp-80a h8/534 hd6475348tf japan pin 1 h8/536 hd6475368tf japan pin 1 tqfp-80c figure 1-4 pin arrangement (fp-80a, tfp-80c, top view) 8
1.3.2 pin functions pin arrangements in each operating mode: table 1-2 lists the arrangements of the pins of the cp-84 and cg-84 packages in each operating mode. table 1-3 lists the arrangements for the fp-80a package. table 1-2 pin arrangements in each operating mode (cp-84, cg-84) notes: 1. for the prom mode, see section 17, ?om. 2. pins marked nc should be left unconnected. pin name expanded minimum expanded maximum single-chip prom pin modes modes mode mode no. mode 1 mode 2 mode 3 mode 4 mode 7 h8/534 h8/536 1 xtal xtal xtal xtal xtal nc nc 2 v ss v ss v ss v ss v ss v ss v ss 3 p1 0 /? p1 0 /? p1 0 /? p1 0 /? p1 0 /? nc nc 4 p1 1 /e p1 1 /e p1 1 /e p1 1 /e p1 1 /e nc nc 5 p1 2 / back p1 2 / back p1 2 / back p1 2 / back p1 2 nc nc 6 p1 3 / breq p1 3 / breq p1 3 / breq p1 3 / breq p1 3 nc nc 7 p1 4 / wait p1 4 / wait p1 4 / wait p1 4 / wait p1 4 nc a 15 8 p1 5 / irq 0 p1 5 / irq 0 p1 5 / irq 0 p1 5 / irq 0 p1 5 / irq 0 nc a 16 9 p1 6 / irq 1 / p1 6 / irq 1 / p1 6 / irq 1 / p1 6 / irq 1 / p1 6 / irq 1 / nc pgm adtrg adtrg adtrg adtrg adtrg 10 p1 7 / tmo p1 7 / tmo p1 7 / tmo p1 7 / tmo p1 7 / tmo nc nc 11 as as as as p2 0 nc nc 12 r/w r/w r/w r/w p2 1 nc nc 13 ds ds ds ds p2 2 nc nc 14 rd rd rd rd p2 3 nc nc 15 wr wr wr wr p2 4 nc nc 16 v cc v cc v cc v cc v cc v cc v cc 17 md 0 md 0 md 0 md 0 md 0 v ss v ss 18 md 1 md 1 md 1 md 1 md 1 v ss v ss 9
table 1-2 pin arrangements in each operating mode (cp-84, cg-84) (cont) notes: 1. for the prom mode, see section 17, ?om. 2. pins marked nc should be left unconnected. pin name expanded minimum expanded maximum single-chip prom pin modes modes mode mode no. mode 1 mode 2 mode 3 mode 4 mode 7 h8/534 h8/536 19 md 2 md 2 md 2 md 2 md 2 v ss v ss 20 stby stby stby stby stby v ss v ss 21 res res res res res v pp v pp 22 nmi nmi nmi nmi nmi a 9 a 9 23 nc nc nc nc nc nc nc 24 v ss v ss v ss v ss v ss v ss v ss 25 d 0 d 0 d 0 d 0 p3 0 o 0 o 0 26 d 1 d 1 d 1 d 1 p3 1 o 1 o 1 27 d 2 d 2 d 2 d 2 p3 2 o 2 o 2 28 d 3 d 3 d 3 d 3 p3 3 o 3 o 3 29 d 4 d 4 d 4 d 4 p3 4 o 4 o 4 30 d 5 d 5 d 5 d 5 p3 5 o 5 o 5 31 d 6 d 6 d 6 d 6 p3 6 o 6 o 6 32 d 7 d 7 d 7 d 7 p3 7 o 7 o 7 33 a 0 a 0 a 0 a 0 p4 0 a 0 a 0 34 a 1 a 1 a 1 a 1 p4 1 a 1 a 1 35 a 2 a 2 a 2 a 2 p4 2 a 2 a 2 36 a 3 a 3 a 3 a 3 p4 3 a 3 a 3 37 a 4 a 4 a 4 a 4 p4 4 a 4 a 4 38 a 5 a 5 a 5 a 5 p4 5 a 5 a 5 39 a 6 a 6 a 6 a 6 p4 6 a 6 a 6 40 a 7 a 7 a 7 a 7 p4 7 a 7 a 7 41 v ss v ss v ss v ss v ss v ss v ss 10
table 1-2 pin arrangements in each operating mode (cp-84, cg-84) (cont) notes: 1. for the prom mode, see section 17, ?om. 2. pins marked nc should be left unconnected. pin name expanded minimum expanded maximum single-chip prom pin modes modes mode mode no. mode 1 mode 2 mode 3 mode 4 mode 7 h8/534 h8/536 42 v ss v ss v ss v ss v ss v ss v ss 43 a 8 p5 0 / a 8 a 8 p5 0 / a 8 p5 0 a 8 a 8 44 a 9 p5 1 / a 9 a 9 p5 1 / a 9 p5 1 oe oe 45 a 10 p5 2 / a 10 a 10 p5 2 / a 10 p5 2 a 10 a 10 46 a 11 p5 3 / a 11 a 11 p5 3 / a 11 p5 3 a 11 a 11 47 a 12 p5 4 / a 12 a 12 p5 4 / a 12 p5 4 a 12 a 12 48 a 13 p5 5 / a 13 a 13 p5 5 / a 13 p5 5 a 13 a 13 49 a 14 p5 6 / a 14 a 14 p5 6 / a 14 p5 6 a 14 a 14 50 a 15 p5 7 / a 15 a 15 p5 7 / a 15 p5 7 ce ce 51 p6 0 / irq 2 p6 0 / irq 2 a 16 p6 0 / irq 2 / p6 0 / irq 2 v cc v cc a 16 52 p6 1 / pw 1 / p6 1 / pw 1 / a 17 p6 1 / irq 3 / p6 1 / pw 1 / v cc v cc irq 3 irq 3 a 17 irq 3 53 p6 2 / pw 2 / p6 2 / pw 2 / a 18 p6 2 / irq 4 / p6 2 / pw 2 / nc nc irq 4 irq 4 a 18 irq 4 54 p6 3 / pw 3 / p6 3 / pw 3 / a 19 p6 3 / irq 5 / p6 3 / pw 3 / nc nc irq 5 irq 5 a 19 irq 5 55 v cc v cc v cc v cc v cc v cc v cc 56 p7 0 / tmci p7 0 / tmci p7 0 / tmci p7 0 / tmci p7 0 / tmci nc nc 57 p7 1 / fti 1 p7 1 / fti 1 p7 1 / fti 1 p7 1 / fti 1 p7 1 / fti 1 nc nc 58 p7 2 / fti 2 p7 2 / fti 2 p7 2 / fti 2 p7 2 / fti 2 p7 2 / fti 2 nc nc 59 p7 3 / fti 3 / p7 3 / fti 3 / p7 3 / fti 3 / p7 3 / fti 3 / p7 3 / fti 3 / nc nc tmri tmri tmri tmri tmri 60 p7 4 / ftob 1 / p7 4 / ftob 1 / p7 4 / ftob 1 / p7 4 / ftob 1 / p7 4 / ftob 1 / nc nc ftci 1 ftci 1 ftci 1 ftci 1 ftci 1 61 p7 5 / ftob 2 / p7 5 / ftob 2 / p7 5 / ftob 2 / p7 5 / ftob 2 / p7 5 / ftob 2 / nc nc ftci 2 ftci 2 ftci 2 ftci 2 ftci 2 11
table 1-2 pin arrangements in each operating mode (cp-84, cg-84) (cont) notes: 1. for the prom mode, see section 17, ?om. 2. pins marked nc should be left unconnected. pin name expanded minimum expanded maximum single-chip prom pin modes modes mode mode no. mode 1 mode 2 mode 3 mode 4 mode 7 h8/534 h8/536 62 p7 6 / ftob 3 / p7 6 / ftob 3 / p7 6 / ftob 3 / p7 6 / ftob 3 / p7 6 / ftob 3 / nc nc ftci 3 ftci 3 ftci 3 ftci 3 ftci 3 63 p7 7 / ftoa 1 p7 7 / ftoa 1 p7 7 / ftoa 1 p7 7 / ftoa 1 p7 7 / ftoa 1 nc nc 64 v ss v ss v ss v ss v ss v ss v ss 65 av ss av ss av ss av ss av ss v ss v ss 66 p8 0 / an 0 p8 0 / an 0 p8 0 / an 0 p8 0 / an 0 p8 0 / an 0 nc nc 67 p8 1 / an 1 p8 1 / an 1 p8 1 / an 1 p8 1 / an 1 p8 1 / an 1 nc nc 68 p8 2 / an 2 p8 2 / an 2 p8 2 / an 2 p8 2 / an 2 p8 2 / an 2 nc nc 69 p8 3 / an 3 p8 3 / an 3 p8 3 / an 3 p8 3 / an 3 p8 3 / an 3 nc nc 70 p8 4 / an 4 p8 4 / an 4 p8 4 / an 4 p8 4 / an 4 p8 4 / an 4 nc nc 71 p8 5 / an 5 p8 5 / an 5 p8 5 / an 5 p8 5 / an 5 p8 5 / an 5 nc nc 72 p8 6 / an 6 p8 6 / an 6 p8 6 / an 6 p8 6 / an 6 p8 6 / an 6 nc nc 73 p8 7 / an 7 p8 7 / an 7 p8 7 / an 7 p8 7 / an 7 p8 7 / an 7 nc nc 74 av cc av cc av cc av cc av cc v cc v cc 75 p9 0 / ftoa 2 p9 0 / ftoa 2 p9 0 / ftoa 2 p9 0 / ftoa 2 p9 0 / ftoa 2 nc nc 76 p9 1 / ftoa 3 p9 1 / ftoa 3 p9 1 / ftoa 3 p9 1 / ftoa 3 p9 1 / ftoa 3 nc nc 77 p9 2 / txd 2 / p9 2 / txd 2 / p9 2 / txd 2 / p9 2 / txd 2 / p9 2 / txd 2 / nc nc pw 1 pw 1 pw 1 pw 1 pw 1 78 p9 3 / rxd 2 / p9 3 / rxd 2 / p9 3 / rxd 2 / p9 3 / rxd 2 / p9 3 / rxd 2 / nc nc pw 2 pw 2 pw 2 pw 2 pw 2 79 p9 4 / sck 2 / p9 4 / sck 2 / p9 4 / sck 2 / p9 4 / sck 2 / p9 4 / sck 2 / nc nc pw 3 pw 3 pw 3 pw 3 pw 3 80 p9 5 / txd 1 p9 5 / txd 1 p9 5 / txd 1 p9 5 / txd 1 p9 5 / txd 1 nc nc 81 p9 6 / rxd 1 p9 6 / rxd 1 p9 6 / rxd 1 p9 6 / rxd 1 p9 6 / rxd 1 nc nc 82 p9 7 / sck 1 p9 7 / sck 1 p9 7 / sck 1 p9 7 / sck 1 p9 7 / sck 1 nc nc 83 v ss v ss v ss v ss v ss v ss v ss 84 extal extal extal extal extal nc nc 12
table 1-3 pin arrangements in each operating mode (fp-80a, tfp-80c) notes: 1. for the prom mode, see section 17, ?om. 2. pins marked nc should be left unconnected. pin name expanded minimum expanded maximum single-chip prom pin modes modes mode mode no. mode 1 mode 2 mode 3 mode 4 mode 7 h8/534 h8/536 1 r/w r/w r/w r/w p2 1 nc nc 2 ds ds ds ds p2 2 nc nc 3 rd rd rd rd p2 3 nc nc 4 wr wr wr wr p2 4 nc nc 5 v cc v cc v cc v cc v cc v cc v cc 6 md 0 md 0 md 0 md 0 md 0 v ss v ss 7 md 1 md 1 md 1 md 1 md 1 v ss v ss 8 md 2 md 2 md 2 md 2 md 2 v ss v ss 9 stby stby stby stby stby v ss v ss 10 res res res res res v pp v pp 11 nmi nmi nmi nmi nmi a 9 a 9 12 v ss v ss v ss v ss v ss v ss v ss 13 d 0 d 0 d 0 d 0 p3 0 o 0 o 0 14 d 1 d 1 d 1 d 1 p3 1 o 1 o 1 15 d 2 d 2 d 2 d 2 p3 2 o 2 o 2 16 d 3 d 3 d 3 d 3 p3 3 o 3 o 3 17 d 4 d 4 d 4 d 4 p3 4 o 4 o 4 18 d 5 d 5 d 5 d 5 p3 5 o 5 o 5 19 d 6 d 6 d 6 d 6 p3 6 o 6 o 6 20 d 7 d 7 d 7 d 7 p3 7 o 7 o 7 21 a 0 a 0 a 0 a 0 p4 0 a 0 a 0 13
table 1-3 pin arrangements in each operating mode (fp-80a, tfp-80c) (cont) notes: 1. for the prom mode, see section 17, ?om. 2. pins marked nc should be left unconnected. pin name expanded minimum expanded maximum single-chip prom pin modes modes mode mode no. mode 1 mode 2 mode 3 mode 4 mode 7 h8/534 h8/536 22 a 1 a 1 a 1 a 1 p4 1 a 1 a 1 23 a 2 a 2 a 2 a 2 p4 2 a 2 a 2 24 a 3 a 3 a 3 a 3 p4 3 a 3 a 3 25 a 4 a 4 a 4 a 4 p4 4 a 4 a 4 26 a 5 a 5 a 5 a 5 p4 5 a 5 a 5 27 a 6 a 6 a 6 a 6 p4 6 a 6 a 6 28 a 7 a 7 a 7 a 7 p4 7 a 7 a 7 29 v ss v ss v ss v ss v ss v ss v ss 30 a 8 p5 0 / a 8 a 8 p5 0 / a 8 p5 0 a 8 a 8 31 a 9 p5 1 / a 9 a 9 p5 1 / a 9 p5 1 oe oe 32 a 10 p5 2 / a 10 a 10 p5 2 / a 10 p5 2 a 10 a 10 33 a 11 p5 3 / a 11 a 11 p5 3 / a 11 p5 3 a 11 a 11 34 a 12 p5 4 / a 12 a 12 p5 4 / a 12 p5 4 a 12 a 12 35 a 13 p5 5 / a 13 a 13 p5 5 / a 13 p5 5 a 13 a 13 36 a 14 p5 6 / a 14 a 14 p5 6 / a 14 p5 6 a 14 a 14 37 a 15 p5 7 / a 15 a 15 p5 7 / a 15 p5 7 ce ce 38 p6 0 / irq 2 p6 0 / irq 2 a 16 p6 0 / irq 2 / p6 0 / irq 2 v cc v cc a 16 39 p6 1 / pw 1 / p6 1 / pw 1 / a 17 p6 1 / irq 3 / p6 1 / pw 1 / v cc v cc irq 3 irq 3 a 17 irq 3 40 p6 2 / pw 2 / p6 2 / pw 2 / a 18 p6 2 / irq 4 / p6 2 / pw 2 / nc nc irq 4 irq 4 a 18 irq 4 41 p6 3 / pw 3 / p6 3 / pw 3 / a 19 p6 3 / irq 5 / p6 3 / pw 3 / nc nc irq 5 irq 5 a 19 irq 5 42 v cc v cc v cc v cc v cc v cc v cc 14
table 1-3 pin arrangements in each operating mode (fp-80a, tfp-80c) (cont) notes: 1. for the prom mode, see section 17, ?om. 2. pins marked nc should be left unconnected. pin name expanded minimum expanded maximum single-chip prom pin modes modes mode mode no. mode 1 mode 2 mode 3 mode 4 mode 7 h8/534 h8/536 43 p7 0 / tmci p7 0 / tmci p7 0 / tmci p7 0 / tmci p7 0 / tmci nc nc 44 p7 1 / fti 1 p7 1 / fti 1 p7 1 / fti 1 p7 1 / fti 1 p7 1 / fti 1 nc nc 45 p7 2 / fti 2 p7 2 / fti 2 p7 2 / fti 2 p7 2 / fti 2 p7 2 / fti 2 nc nc 46 p7 3 / fti 3 / p7 3 / fti 3 / p7 3 / fti 3 / p7 3 / fti 3 / p7 3 / fti 3 / nc nc tmri tmri tmri tmri tmri 47 p7 4 / ftob 1 / p7 4 / ftob 1 / p7 4 / ftob 1 / p7 4 / ftob 1 / p7 4 / ftob 1 / nc nc ftci 1 ftci 1 ftci 1 ftci 1 ftci 1 48 p7 5 / ftob 2 / p7 5 / ftob 2 / p7 5 / ftob 2 / p7 5 / ftob 2 / p7 5 / ftob 2 / nc nc ftci 2 ftci 2 ftci 2 ftci 2 ftci 2 49 p7 6 / ftob 3 / p7 6 / ftob 3 / p7 6 / ftob 3 / p7 6 / ftob 3 / p7 6 / ftob 3 / nc nc ftci 3 ftci 3 ftci 3 ftci 3 ftci 3 50 p7 7 / ftoa 1 p7 7 / ftoa 1 p7 7 / ftoa 1 p7 7 / ftoa 1 p7 7 / ftoa 1 nc nc 51 av ss av ss av ss av ss av ss v ss v ss 52 p8 0 / an 0 p8 0 / an 0 p8 0 / an 0 p8 0 / an 0 p8 0 / an 0 nc nc 53 p8 1 / an 1 p8 1 / an 1 p8 1 / an 1 p8 1 / an 1 p8 1 / an 1 nc nc 54 p8 2 / an 2 p8 2 / an 2 p8 2 / an 2 p8 2 / an 2 p8 2 / an 2 nc nc 55 p8 3 / an 3 p8 3 / an 3 p8 3 / an 3 p8 3 / an 3 p8 3 / an 3 nc nc 56 p8 4 / an 4 p8 4 / an 4 p8 4 / an 4 p8 4 / an 4 p8 4 / an 4 nc nc 57 p8 5 / an 5 p8 5 / an 5 p8 5 / an 5 p8 5 / an 5 p8 5 / an 5 nc nc 58 p8 6 / an 6 p8 6 / an 6 p8 6 / an 6 p8 6 / an 6 p8 6 / an 6 nc nc 59 p8 7 / an 7 p8 7 / an 7 p8 7 / an 7 p8 7 / an 7 p8 7 / an 7 nc nc 15
table 1-3 pin arrangements in each operating mode (fp-80a, tfp-80c) (cont) notes: 1. for the prom mode, see section 17, ?om. 2. pins marked nc should be left unconnected. pin name expanded minimum expanded maximum single-chip prom pin modes modes mode mode no. mode 1 mode 2 mode 3 mode 4 mode 7 h8/534 h8/536 60 av cc av cc av cc av cc av cc v cc v cc 61 p9 0 / ftoa 2 p9 0 / ftoa 2 p9 0 / ftoa 2 p9 0 / ftoa 2 p9 0 / ftoa 2 nc nc 62 p9 1 / ftoa 3 p9 1 / ftoa 3 p9 1 / ftoa 3 p9 1 / ftoa 3 p9 1 / ftoa 3 nc nc 63 p9 2 / pw 1 p9 2 / pw 1 p9 2 / pw 1 p9 2 / pw 1 p9 2 / pw 1 nc nc 64 p9 3 / pw 2 p9 3 / pw 2 p9 3 / pw 2 p9 3 / pw 2 p9 3 / pw 2 nc nc 65 p9 4 / pw 3 p9 4 / pw 3 p9 4 / pw 3 p9 4 / pw 3 p9 4 / pw 3 nc nc 66 p9 5 / txd p9 5 / txd p9 5 / txd p9 5 / txd p9 5 / txd nc nc 67 p9 6 / rxd p9 6 / rxd p9 6 / rxd p9 6 / rxd p9 6 / rxd nc nc 68 p9 7 / sck p9 7 / sck p9 7 / sck p9 7 / sck p9 7 / sck nc nc 69 extal extal extal extal extal nc nc 70 xtal xtal xtal xtal xtal nc nc 71 v ss v ss v ss v ss v ss v ss v ss 72 p1 0 / ? p1 0 / ? p1 0 / ? p1 0 / ? p1 0 / ? nc nc 73 p1 1 / e p1 1 / e p1 1 / e p1 1 / e p1 1 / e nc nc 74 p1 2 / back p1 2 / back p1 2 / back p1 2 / back p1 2 nc nc 75 p1 3 / breq p1 3 / breq p1 3 / breq p1 3 / breq p1 3 nc nc 76 p1 4 / wait p1 4 / wait p1 4 / wait p1 4 / wait p1 4 nc a 15 77 p1 5 / irq 0 p1 5 / irq 0 p1 5 / irq 0 p1 5 / irq 0 p1 5 / irq 0 nc a 16 78 p1 6 / irq 1 / p1 6 / irq 1 / p1 6 / irq 1 / p1 6 / irq 1 / p1 6 / irq 1 / nc pgm adtrg adtrg adtrg adtrg adtrg 79 p1 7 / tmo p1 7 / tmo p1 7 / tmo p1 7 / tmo p1 7 / tmo nc nc 80 as as as as p2 0 nc nc 16
pin functions: table 1-4 gives a concise description of the function of each pin. table 1-4 pin functions pin no. cp-84, fp-80a, type symbol cg-84 tfp-80c i/o name and function power v cc 16, 55 5, 42 i power: connected to the power supply (+5 v). connect both v cc pins to the system power supply (+5 v). the chip will not operate if either pin is left unconnected. v ss 2, 24 12, 29 i ground: connected to ground (0 v). 41, 42 71 connect all v ss pins to the system power 64, 83 supply (0 v). the chip will not operate if any v ss pin is left unconnected. clock xtal 1 70 i crystal: connected to a crystal oscillator. the crystal frequency should be double the desired ?clock frequency. if an external clock is input at the extal pin, leave the xtal pin unconnected. extal 84 69 i external crystal: connected to a crystal oscillator or external clock. the frequency of the external clock should be double the desired ?clock frequency. see section 8.2, ?scillator circuit?for examples of connections to a crystal and external clock. ? 3 72 o system clock: supplies the ?clock to peripheral devices. e 4 73 o enable clock: supplies an e clock to e clock based peripheral devices. system back 5 74 o bus request acknowledge: indicates control that the bus right has been granted to an external device. notifies an external device that issued a breq signal that it now has control of the bus. 17
table 1-4 pin functions (cont) pin no. cp-84, fp-80a, type symbol cg-84 tfp-80c i/o name and function system breq 6 75 i bus request: sent by an external device to the control h8/534 or h4/536 to request the bus right. stby 20 9 i standby: a transition to the hardware standby mode (a power-down state) occurs when a low input is received at the stby pin. res 21 10 i/o reset: low input or low output due to watchdog timer overflow causes the h8/534 or h8/536 chip to reset. address a 19 ?a 8 54 ?43 41 ?30 o address bus: address output pins. bus a 7 ?a 0 40 ?33 28 ?21 data bus d 7 ?d 0 32 ?25 20 ?13 i/o data bus: 8-bit bidirectional data bus. bus wait 7 76 i wait: requests the cpu to insert one or more tw control states when accessing an off-chip address. as 11 80 o address strobe: goes low to indicate that there is a valid address on the address bus. r/w 12 1 o read/write: indicates whether the cpu is reading or writing data on the bus. ? high?ead ? low?rite ds 13 2 o data strobe: goes low to indicate the presence of valid data on the data bus. rd 14 3 o read: goes low to indicate that the cpu is reading an external address. wr 15 4 o write: goes low to indicate that the cpu is writing to an external address. 18
table 1-4 pin functions (cont) pin no. cp-84, fp-80a, type symbol cg-84 tfp-80c i/o name and function interrupt nmi 22 11 i nonmaskable interrupt: highest-priority interrupt request. the port 1 control register (p1cr) determines whether the interrupt is requested on the rising or falling edge of the nmi input. irq 0 8 77 i interrupt request 0 and 1: maskable interrupt irq 1 9 78 request pins. irq 2 51 38 irq 3 52 39 irq 4 53 40 irq 5 54 41 operatingmd 2 19 8 i mode: input pins for setting the mcu operating mode md 1 18 7 mode according to the table below. control md 0 17 6 md 2 md 1 md 0 mode description 0 0 0 mode 0 0 0 1 mode 1 expanded minimum mode (rom disabled) 0 1 0 mode 2 expanded minimum mode (rom enabled) 0 1 1 mode 3 expanded maximum mode (rom disabled) 1 0 0 mode 4 expanded maximum mode (rom enabled) 1 0 1 mode 5 1 1 0 mode 6 1 1 1 mode 7 single-chip mode the inputs at these pins must not be changed while the chip is operating. 19
table 1-4 pin functions (cont) pin no. cp-84, fp-80a, type symbol cg-84 tfp-80c i/o name and function 16-bit free- ftoa 1 63 50 o frt output compare a (channels 1, 2, and 3): running ftoa 2 75 61 output pins for the output compare a function timer (frt) ftoa 3 76 62 of free-running timer channels 1, 2, and 3. ftob 1 60 47 o frt output compare b (channels 1, 2, and 3): ftob 2 61 48 output pins for the output compare b function ftob 3 62 49 of free-running timer channels 1, 2, and 3. ftci 1 60 47 i frt counter clock input (channels 1, 2, and 3): ftci 2 61 48 external clock input pins for the free-running ftci 3 62 49 counters (frcs) of free-running timer channels 1, 2, and 3. fti 1 57 44 i frt input capture (channels 1, 2, and 3): fti 2 58 45 input capture pins for free-running timer fti 3 59 46 channels 1, 2, and 3. 8-bit tmo 10 79 o 8-bit timer output: compare-match output pin timer for the 8-bit timer. tmci 56 43 i 8-bit timer clock input: external clock input pin for the 8-bit timer counter. tmri 59 46 i 8-bit timer counter reset input: a high input at this pin resets the 8-bit timer counter. pwm pw 1 77 63 o pwm timer output (channels 1, 2, and 3): timer pw 2 78 64 pulse-width modulation timer output pulses. pw 3 79 65 20
table 1-4 pin functions (cont) pin no. cp-84, fp-80a, type symbol cg-84 tfp-80c i/o name and function serial com- txd 1 80 66 o transmit data: data output pins for serial munication txd 2 77 63 communication interfaces 1 and 2. interface rxd 1 81 67 i receive data: data input pins for serial signals rxd 2 78 64 communication interfaces 1 and 2. sck 1 82 68 i/o serial clock: input/output pins for the serial sck 2 79 65 clock of serial interface 1 and 2. a/d an 7 ?an 0 73 ?66 59 ?52 i analog input: analog signal input pins. converter av cc 74 60 i analog reference voltage: reference voltage and power supply pin for the a/d converter. av ss 65 51 i analog ground: ground pin for the a/d converter. adtrg 9 78 i external trigger: external trigger input pin for the a/d converter. parallel p1 7 ?p1 0 10 ?3 79 ?72 i/o port 1: an 8-bit input/output port. the i/o direction of each bit is determined by the port 1 data direction register (p1ddr). p2 4 ?p2 0 15 ?11 4 ?1, i/o port 2: a 5-bit input/output port. the 80 direction of each bit is determined by the port 2 data direction register (p2ddr). p3 7 ?p3 0 32 ?25 20 ?13 i/o port 3: an 8-bit input/output port. the direction of each bit is determined by the port 3 data direction register (p3ddr). p4 7 ?p4 0 40 ?33 28 ?21 i/o port 4: an 8-bit input/output port. the direction of each bit is determined by the port 4 data direction register (p4ddr). these pins can drive led indicators. 21
table 1-4 pin functions (cont) pin no. cp-84, fp-80a, type symbol cg-84 tfp-80c i/o name and function parallel p5 7 ?p5 0 50 ?43 37 ?30 i/o port 5: an 8-bit input/output port. i/o the direction of each bit is determined by the port 5 data direction register (p5ddr). these pins have built-in mos input pull-ups. p6 3 ?p6 0 54 ?51 41 ?38 i/o port 6: a 4-bit input/output port. the direction of each bit is determined by the port 6 data direction register (p6ddr). these pins have built-in mos input pull-ups. p7 7 ?p7 0 63 ?56 50 ?43 i/o port 7: an 8-bit input/output port. the direction of each bit is determined by the port 7 data direction register (p7ddr). these pins have schmitt inputs. p8 7 ?p8 0 73 ?66 59 ?52 i port 8: an 8-bit input port p9 7 ?p9 0 82 ?75 68 ?61 i/o port 9: an 8-bit input/output port. the direction of each bit is determined by the port 9 data direction register (p9ddr). 22
section 2 mcu operating modes and address space 2.1 overview the h8/534 or h8/536 microcomputer unit (mcu) operates in five modes numbered 1, 2, 3, 4, and 7. the mode is selected by the inputs at the mode pins (md 2 to md 0 ) at the instant when the chip comes out of a reset. as indicated in table 2-1, the mcu mode determines the size of the address space, the usage of on-chip rom, and the operating mode of the cpu. the mcu mode also affects the functions of i/o pins. table 2-1 operating modes md 2 md 1 md 0 mcu mode address space on-chip rom cpu mode 0 0 0 0 0 1 mode 1 expanded minimum disabled minimum mode 0 1 0 mode 2 expanded minimum enabled minimum mode 0 1 1 mode 3 expanded maximum disabled maximum mode 1 0 0 mode 4 expanded maximum enabled maximum mode 1 0 1 1 1 0 1 1 1 mode 7 single-chip only enabled minimum mode notation: 0: low level 1: high level ? cannot be used modes 1 to 4 are referred to as ?xpanded?because they permit access to off-chip memory and peripheral addresses. the expanded minimum modes (modes 1 and 2) support a maximum address space of 64 kbytes. the expanded maximum modes (modes 3 and 4) support a maximum address space of 1 mbyte. interrupt service is slightly slower in the expanded maximum modes than in the other modes because the cpu has to save its code page register. in single-chip mode all ports are available for general-purpose input and output, but off-chip addresses cannot be accessed. the h8/534 and h8/536 cannot be set to modes 0, 5, and 6. the mode pins should never be set to these values. the inputs at the mode pins must not be changed while the chip is operating. 23
2.2 mode descriptions the five mcu modes are described below. for further information on the i/o pin functions in each mode, see section 9, ?/o ports. mode 1 (expanded minimum mode): mode 1 supports a maximum 64-kbyte address space which does not include any on-chip rom. ports 1 to 5 are used for bus lines and bus control signals as follows: control signals: ports 1* and 2 data bus: port 3 address bus: ports 4 and 5 * the functions of individual pins of port 1 are software-selectable. mode 2 (expanded minimum mode): mode 2 supports a maximum 64-kbyte address space of which the first part is in on-chip rom. ports 1 to 5 are used for bus lines and bus control signals as follows: control signals: ports 1* and 2 data bus: port 3 address bus: ports 4 and 5* * the functions of individual pins in ports 1 and 5 are software-selectable. note: in mode 2, port 5 is initially a general-purpose input port. software must change it to output before using it for the address bus. see section 9.6, ?ort 5?for details. the following instruction makes all pins of port 5 into output pins: mov.b #h'ff, @h'fe88* * h'xx or h'xxxx express the hexadecimal number. mode 3 (expanded maximum mode): mode 3 supports a maximum 1-mbyte address space which does not include any on-chip rom. ports 1 to 6 are used for bus lines and bus control signals as follows: control signals: ports 1* and 2 data bus: port 3 address bus: ports 4, 5, and 6 * the functions of individual pins of port 1 are software-selectable. 24
mode 4 (expanded maximum mode): mode 4 supports a maximum 1-mbyte address space of which the first part is in on-chip rom. ports 1 to 6 are used for bus lines and bus control signals as follows: control signals: ports 1* and 2 data bus: port 3 address bus: ports 4, 5*, and 6* * the functions of individual pins in ports 1, 5, and 6 are software-selectable. note: in mode 4, ports 5 and 6 are initially general-purpose input ports. software must change them to output before using them for the address bus. see section 9.6, ?ort 5?and 10.7, ?ort 6 for details. the following instruction sets all pins of ports 5 and 6 to output: mov.w #h'ffff, @h'fe88 mode 7 (single-chip mode): in this mode all memory is on-chip. it is not possible to access off-chip addresses. the single-chip mode provides the maximum number of ports. all the pins associated with the address and data buses in the expanded modes are available as general-purpose input/output ports in the single-chip mode. 2.3 address space map 2.3.1 page segmentation the address space is segmented into 64-kbyte pages. in the single-chip mode and expanded minimum modes there is just one page: page 0. in the expanded maximum modes there can be up to 16 pages. figure 2-1 shows the address space of the h8/534 in each mode and indicates which parts are on- and off-chip. figure 2-2 shows the address space of the h8/536. 25
2.3.2 page 0 address allocations the high and low address areas in page 0 are reserved for registers and vector tables. vector tables: the low address area contains the exception vector table and dtc vector table. the cpu accesses the exception vector table to obtain the addresses of user-coded exception- handling routines. the dtc vector table contains pointers to tables of register information used by the on-chip chip data transfer controller. the size of these tables depends on the cpu operating mode. details are given in section 4.1.3, ?xception factors and vector table,?section 5.2.3, ?nterrupt vector table,?and section 6.3.2, ?tc vector table. in modes 2 and 4 the vector tables are located in on-chip rom. in modes 1, 3, and 7 the vector tables are in external memory. register field: the highest 384 addresses in page 0 (addresses h'fe80 to h'ffff) belong to control, status, and data registers used by the i/o ports and on-chip supporting modules. program code cannot be located at these addresses. the cpu accesses addresses in this register field like other addresses in the address space. by reading and writing at these addresses the cpu controls the on-chip supporting modules and communicates via the i/o ports. a complete map of the register field is given in appendix b. on-chip ram: one of the control registers in the register field is a ram control register (ramcr) containing a ram enable bit (rame) that enables or disables the 2-kbyte on-chip ram. when this bit is set to 1 (its default value), addresses h'f680 to h'fe7f are located on- chip. when this bit is cleared to 0, these addresses are located in external memory and the on-chip ram is not used. see section 16, ?am?for further information. the rame bit is bit 7 at address h'ff11. coding example: to enable on-chip ram: bset.b #7, @h'ff11 to disable on-chip ram: bclr.b #7, @h'ff11 note: if on-chip ram is disabled in the single-chip mode, access to addresses h'f680 to h'fe7f causes an address error. 26
2.4 mode control register (mdcr) another control register in the register field in page 0 is the mode control register (mdcr). the mode control register can be read by the cpu, but not written. table 3-2 lists the attributes of this register. table 2-2 mode control register name abbreviation read/write address mode control register mdcr read only h'ff12 the bit configuration of this register is shown below. * initialized according to md 2 to md 0 . bits 7 and 6?eserved: these bits cannot be modified and are always read as 1. bits 5 to 3?eserved: these bits cannot be modified and are always read as 0. bits 2 to 0?ode select 2 to 0 (mds2 to mds0): these bits indicate the values of the mode pins (md 2 to md 0 ) latched on the rising edge of the signal. mds2 corresponds to md 2 , mds1 to md 1 , and mds0 to md 0 . these bits can be read but not written. coding example: to test whether the mcu is operating in mode 1: cmp:g.b #h'c1, @h'ff12 the comparison is with h'c1 instead of h'01 because bits 7 and 6 are always read as 1. bit 7 6 5 4 3 2 1 0 mds2 mds1 mds0 initial value 1 1 0 0 0 * * * read/write r r r 27
expanded minimum mode expanded maximum mode single-chip mode mode 1 mode 2 mode 3 mode 4 mode 7 vector tables external memory on-chip ram 2 kbytes register field 384 bytes vector tables on-chip rom 32 kbytes external memory on-chip ram 2 kbytes register field 384 bytes vector tables external memory on-chip ram 2 kbytes register field 384 bytes external memory vector tables on-chip rom 32 kbytes external memory on-chip ram 2 kbytes register field 384 bytes external memory vector tables on-chip rom 32 kbytes h'0000 h'00ff h'0100 h'f67f h'f680 h'fe7f h'fe80 h'ffff h'0000 h'00ff h'0100 h'7fff h'8000 page 0 h'f67f h'f680 h'fe7f h'fe80 h'ffff h'00000 h'001ff h'00200 page 0 h'0f67f h'0f680 h'0fe7f h'0fe80 h'0ffff h'10000 h'1ffff h'f0000 h'fffff h'00000 h'001ff h'00200 h'07fff h'08000 page 0 h'0f67f h'0f680 h'0fe7f h'0fe80 h'0ffff h'10000 page 1 h'1ffff h'f0000 page 15 h'fffff h'0000 h'00ff h'0100 h'7fff page 0 h'f680 h'fe7f h'fe80 h'ffff page 1 page 15 page 0 on-chip ram 2 kbytes register field 384 bytes figure 2-1 h8/534 memory map in each operating mode
expanded minimum mode expanded maximum mode single-chip mode mode 1 mode 2 mode 3 mode 4 mode 7 vector tables external memory on-chip ram 2 kbytes register field 384 bytes vector tables on-chip rom 60 kbytes external memory on-chip ram 2 kbytes register field 384 bytes vector tables external memory on-chip ram 2 kbytes register field 384 bytes external memory vector tables on-chip rom 62 kbytes on-chip ram 2 kbytes register field 384 bytes external memory vector tables on-chip rom 62 kbytes on-chip ram 2 kbytes register field 384 bytes h'0000 h'00ff h'0100 h'f67f h'f680 h'fe7f h'fe80 h'ffff h'0000 h'00ff h'0100 h'ee7f page 0 h'ee80 h'f67f h'f680 h'fe7f h'fe80 h'ffff h'00000 h'001ff h'00200 page 0 h'0f67f h'0f680 h'0fe7f h'0fe80 h'0ffff h'10000 h'1ffff h'f0000 h'fffff h'00000 h'001ff h'00200 page 0 h'0f67f h'0f680 h'0fe7f h'0fe80 h'0ffff h'10000 page 1 h'1ffff h'f0000 page 15 h'fffff h'0000 h'00ff h'0100 page 0 h'f67f h'f680 h'fe7f h'fe80 h'ffff page 1 page 15 page 0 figure 2-2 h8/536 memory map in each operating mode
section 3 cpu 3.1 overview the h8/534 and h8/536 have the h8/500 family cpu: a high-speed central processing unit designed for realtime control of a wide range of medium-scale office and industrial equipment. its hitachi-original architecture features eight 16-bit general registers, internal 16-bit data paths, and an optimized instruction set. section 3 summarizes the cpu architecture and instruction set. 3.1.1 features the main features of the h8/500 cpu are listed below. general-register machine ?eight 16-bit general registers ?seven control registers (two 16-bit registers, five 8-bit registers) high speed: maximum 16 mhz (s-mask versions) at 16 mhz a register-register add operation takes only 125 ns. address space managed in 64-kbyte pages, expandable to 1 mbyte* page registers make four pages available simultaneously: a code page, stack page, data page, and extended page. two cpu operating modes: ?minimum mode: maximum 64-kbyte address space ?maximum mode: maximum 1 mbyte address space* highly orthogonal instruction set addressing modes and data sizes can be specified independently within each instruction. 1.5 addressing modes register-register and register-memory operations are supported. optimized for efficient programming in c language in addition to the general registers and orthogonal instruction set, the cpu has special short formats for frequently-used instructions and addressing modes. * the cpu architecture supports up to 16 mbytes of external memory, but the h8/534 and h8/536 have only enough address pins to address 1 mbyte. 31
3.1.2 address space the address space size depends on the operating mode. the h8/534 or h8/536 mcu has five operating modes, which are selected by the input to the mode pins (md 2 to md 0 ) when the chip comes out of a reset. the cpu, however, has only two operating modes. the mcu operating mode determines the cpu operating mode, which in turn determines the maximum address space size as indicated in figure 3-1. minimum mode cpu operating mode maximum mode maximum address space: 64 kbytes hightest address: h'ffff maximum address space: 1 mbyte hightest address: h'fffff figure 3-1 cpu operating modes 32
3.1.3 register configuration figure 3-2 shows the register structure of the cpu. there are two groups of registers: the general registers (rn) and control registers (cr). r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7 (fp) (sp) p c s r c c r 15 0 15 8 7 0 t i2 i1 i0 n z v c c p d p e p t p b r fp: frame pointer sp: stack pointer pc: program counter sr: status register ccr: condition code register cp: code page register dp: data page register ep: extended page register tp: stack page register br: base register general registers (rn) control registers (cr) 15 0 figure 3-2 registers in the cpu 33
3.2 cpu register descriptions 3.2.1 general registers all eight of the 16-bit general registers are functionally alike; there is no distinction between data registers and address registers. when these registers are accessed as data registers, either byte or word size can be selected. r6 and r7, in addition to functioning as general registers, have special assignments. r7 is the stack pointer, used implicitly in exception handling and subroutine calls. it can be designated by the name sp, which is synonymous with r7. as indicated in figure 3-3, it points to the top of the stack. it is also used implicitly by the ldm and stm instructions, which load and store multiple registers from and to the stack and pre-decrement or post-increment r7 accordingly. r6 functions as a frame pointer (fp). the link and unlk instructions use r6 implicitly to reserve or release a stack frame. sp unused area stack area fig. 3-3 figure 3-3 stack pointer 34
3.2.2 control registers the cpu control registers (cr) include a 16-bit program counter (pc), a 16-bit status register (sr), four 8-bit page registers, and one 8-bit base register (br). program counter (pc): this 16-bit register indicates the address of the next instruction the cpu will execute. status register (sr): this 16-bit register contains internal status information. the lower half of the status register is referred to as the condition code register (ccr): it can be accessed as a separate condition code byte. bit 15?race (t): when this bit is set to 1, the cpu operates in trace mode and generates a trace exception after every instruction. see section 4.4, ?race?for a description of the trace exception-handling sequence. when the value of this bit is 0, instructions are executed in normal continuous sequence. this bit is cleared to 0 at a reset. bits 14 to 11?eserved: these bits cannot be modified and are always read as 0. bits 10 to 8?nterrupt mask (i2, i1, i0): these bits indicate the interrupt request mask level (0 to 7). as shown in table 3-1, an interrupt request is not accepted unless it has a higher level than the value of the mask. a nonmaskable interrupt (nmi), which has level 8, is accepted at any mask level. after an interrupt is accepted, i2, i1, and i0 are changed to the level of the interrupt. table 3-2 indicates the values of the i bits after an interrupt is accepted. a reset sets all three bits (i2, i1, and i0) to 1, masking all interrupts except nmi. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t i2 i1 i0 n z v c ccr 35
table 3-1 interrupt mask levels mask mask bits priority level i2 i1 i0 interrupts accepted high 7 1 1 1 nmi 6 1 1 0 level 7 and nmi 5 1 0 1 levels 6 to 7 and nmi 4 1 0 0 levels 5 to 7 and nmi 3 0 1 1 levels 4 to 7 and nmi 2 0 1 0 levels 3 to 7 and nmi 1 0 0 1 levels 2 to 7 and nmi low 0 0 0 0 levels 1 to 7 and nmi table 3-2 interrupt mask bits after an interrupt is accepted level of interrupt accepted i2 i1 i0 nmi (8) 1 1 1 7 1 1 1 6 1 1 0 5 1 0 1 4 1 0 0 3 0 1 1 2 0 1 0 1 0 0 1 36
bits 7 to 4?eserved: these bits cannot be modified and are always read as 0. bit 3?egative (n): this bit indicates the most significant bit (sign bit) of the result of an instruction. bit 2?ero (z): this bit is set to 1 to indicate a zero result and cleared to 0 to indicate a nonzero result. bit 1?verflow (v): this bit is set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0?arry (c): this bit is set to 1 when a carry or borrow occurs at the most significant bit, and is cleared to 0 (or left unchanged) at other times. the specific changes that occur in the condition code bits when each instruction is executed are listed in appendix a.1 ?nstruction tables.? see the h8/500 series programming manual for further details. page registers: the code page register (cp), data page register (dp), extended page register (ep), and stack page register (tp) are 8-bit registers that are used only in the maximum mode. no use of their contents is made in the minimum mode. in the maximum mode, the page registers combine with the program counter and general registers to generate 24-bit effective addresses as shown in figure 3-4, thereby expanding the program area, data area, and stack area. 37
code page register (cp): the code page register and the program counter combine to generate a 24-bit program code address. in the maximum mode, the code page register is initialized at a reset to a value loaded from the vector table, and both the code page register and program counter cp dp ep tp pc r0 r4 r5 r6 r7 r1 r2 r3 @ aa : 16 page register 8 bits 16 bits 24 bits (effective address) pc or general register figure 3-4 combinations of page registers with other registers 38
are saved and restored in exception handling. data page register (dp): the data page register combines with general registers r0 to r3 to generate a 24-bit effective address. the data page register contains the upper 8 bits of the address. it is used to calculate effective addresses in the register indirect addressing mode using r0 to r3, and in the 16-bit absolute addressing mode (@aa:16). the data page register is rewritten by the ldc instruction. extended page register (ep): the extended page register combines with general register r4 or r5 to generate a 24-bit operand address. the extended page register contains the upper 8 bits of the address. it is used to calculate effective addresses in the register indirect addressing mode using r4 or r5. the extended page can be used as an additional data page. stack page register (tp): the stack page register combines with r6 (fp) or r7 (sp) to generate a 24-bit stack address. the stack page register contains the upper 8 bits of the address. it is used to calculate effective addresses in the register indirect addressing mode using r6 or r7, in exception handling, and subroutine calls. base register (br): this 8-bit register stores the base address used in the short absolute addressing mode (@aa:8). in this addressing mode a 16-bit effective address in page 0 is generated by using the contents of the base register as the upper 8 bits and an address given in the instruction code as the lower 8 bits. see figure 3-5. in the short absolute addressing mode the address is always located in page 0. br @ aa : 8 8 bits 8 bits 16 bits (effective address) figure 3-5 short absolute addressing mode and base register 39
3.2.3 initial register values when the cpu is reset, its internal registers are initialized as shown in table 3-3. note that the stack pointer (r7) and base register (br) are not initialized to fixed values. also, of the page registers used in maximum mode, only the code page register (cp) is initialized; the other three page registers come out of the reset state with undetermined values. accordingly, in the minimum mode the first instruction executed after a reset should initialize the stack pointer. the base register must also be initialized before the short absolute addressing mode (@aa:8) is used. in the maximum mode, the first instruction executed after a reset should initialize the stack page register (tp) and the next instruction should initialize the stack pointer. later instructions should initialize the base register and the other page registers as necessary. 40
table 3-3 initial values of registers 3.3 data formats the h8/500 cpu can process 1-bit data, 4-bit bcd data, 8-bit (byte) data, 16-bit (word) data, and 32-bit (longword) data. ? bit manipulation instructions operate on 1-bit data. ? decimal arithmetic instructions operate on 4-bit bcd data. ? almost all instructions operate on byte and word data. ? multiply and divide instructions operate on longword data. 3.3.1 data formats in general registers data of all the sizes above can be stored in general registers as shown in table 3-4. initial value register minimum mode maximum mode general registers 15 0 undetermined undetermined r7 ?r0 control registers 15 0 loaded from vector table loaded from vector table pc sr ccr 15 8 7 0 h'070x h'070x t????i2i1i0 ????nzvc (x: undetermined) (x: undetermined) 7 0 cp undetermined loaded from vector table 7 0 dp undetermined undetermined 7 0 ep undetermined undetermined 7 0 tp undetermined undetermined 7 0 br undetermined undetermined 41
bit data locations are specified by bit number. bit 15 is the most significant bit. bit 0 is the least significant bit. bcd and byte data are stored in the lower 8 bits of a general register. word data use all 16 bits of a general register. longword data use two general registers: the upper 16 bits are stored in rn (n must be an even number); the lower 16 bits are stored in rn+1. operations performed on bcd data or byte data do not affect the upper 8 bits of the register. table 3-4 general register data formats * for longword data n must be even (0, 2, 4, or 6). 3.3.2 data formats in memory table 3-5 indicates the data formats in memory. instructions that access bit data in memory have byte or word operands. the instruction specifies a bit number to indicate a specific bit in the operand. access to word data in memory must always begin at an even address. access to word data starting at an odd address causes an address error. the upper 8 bits of word data are stored in address n (where n is an even number); the lower 8 bits are stored in address n+1. data type register no. data structure 1-bit bcd byte word longword rn rn rn rn rn * rn+1 * 15 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 8 7 4 3 0 don?-care upper digit lower digit 15 8 7 0 don?-care msb lsb 15 0 msb lsb 31 16 msb upper 16 bits lower 16 bits lsb 15 0 42
table 3-5 data formats in memory when the stack is accessed in exception processing (to save or restore the program counter, code page register, or status register), word access is always performed, regardless of the actual data size. similarly, when the stack is accessed by an instruction using the pre-decrement or post- increment register indirect addressing mode specifying r7 (@?7 or @r7+), which is the stack pointer, word access is performed regardless of the operand size specified in the instruction. an address error will therefore occur if the stack pointer indicates an odd address. programs should be coded so that the stack pointer always indicates an even address. table 3-6 shows the data formats on the stack. data type data format 1-bit (in byte operand data) 1-bit (in word operand data) byte word 7 6 5 4 3 2 1 0 7 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 msb lsb msb lsb upper 8 bits lower 8 bits address n even address odd address address n even address odd address 7 0 43
table 3-6 data formats on the stack 3.4 instructions 3.4.1 basic instruction formats there are two basic cpu instruction formats: the general format and the special format. general format: this format consists of an effective address (ea) field, an effective address extension field, and an operation code (op) field. the effective address is placed before the operation code because this results in faster execution of the instruction. ? effective address field: one byte containing information used to calculate the effective address of an operand. ? effective address extension: zero to two bytes containing a displacement value, immediate data, or an absolute address. the size of the effective address extension is specified in the effective address field. ? operation code: defines the operation to be carried out on the operand located at the address calculated from the effective address information. some instructions (dadd, dsub, movfpe, movtpe) have an extended format in which the operand code is preceded by a one-byte prefix code. data type data format byte data on stack word data on stack msb lsb upper 8 bits lower 8 bits even address odd address even address odd address msb lsb don?-care effective address field effective address extension operation code 44
? (example of prefix code in dadd instruction) special format: in this format the operation code comes first, followed by the effective address field and effective address extension. this format is used in branching instructions, system control instructions, and other instructions that can be executed faster if the operation is specified before the operand. ? operation code: one or two bytes defining the operation to be performed by the instruction. effective address field and effective address extension: zero to three bytes containing information used to calculate an effective address. 3.4.2 addressing modes the cpu supports 7 addressing modes: (1) register direct; (2) register indirect; (3) register indirect with displacement; (4) register indirect with pre-decrement or post-increment; (5) immediate; (6) absolute; and (7) pc-relative. due to the highly orthogonal nature of the instruction set, most instructions having operands can use any applicable addressing mode from (1) through (6). the pc-relative mode (7) is used by branching instructions. in most instructions, the addressing mode is specified in the effective address field. the effective- address extension, if present, contains a displacement, immediate data, or an absolute address. table 3-7 indicates how the addressing mode is specified in the effective address field. operation code effective address field effective address extension effective address prefix code operation code 10100rrr 00000000 10100rrr 45
table 3-7 addressing modes no. addressing mode mnemonic ea field ea extension 1 register direct rn 1 0 1 0 sz r r r none 2 register indirect @rn 1 1 0 1 sz r r r none 3 register indirect @(d:8,rn) 1 1 1 0 sz r r r displacement (1 byte) with displacement @(d:16,rn) 1 1 1 1 sz r r r displacement (2 bytes) 4 register indirect @?n 1 0 1 1 sz r r r with pre-decrement none register indirect @rn+ 1 1 0 0 sz r r r with post-increment 5 immediate #xx:8 0 0 0 0 0 1 0 0 immediate data (1 byte) #xx:16 0 0 0 0 1 1 0 0 immediate data (2 bytes) 6 absolute * 3 @aa:8 0 0 0 0 sz 1 0 1 1-byte absolute address (offset from br) @aa:16 0 0 0 1 sz 1 0 1 2-byte absolute address 7 pc-relative disp no ea field. 1- or 2-byte displacement addressing mode is specified in the operation code. notes: * 1 sz: specifies the operand size. when sz = 0: byte operand when sz = 1: word operand * 2 rrr: register number field, specifying a general register number. 0 0 0 ?r0 0 0 1 ?r1 0 1 0 ?r2 0 1 1 ?r3 1 0 0 ?r4 1 0 1 ?r5 1 1 0 ?r6 1 1 1 ?r7 * 3 the @aa:8 addressing mode is also referred to as the short absolute addressing mode. * 1 * 2 46
3.4.3 effective address calculation table 3-8 explains how the effective address is calculated in each addressing mode. table 3-8 effective address calculation no. addressing mode effective address calculation effective address 1 register direct operand is contents of rn rn 1010sz rrr 2 register indirect 23 15 0 @rn dp * 1 rn 1101sz rrr or tp or ep * 2 3 register indirect 8 bits with displacement 15 0 23 15 0 @(d:8,rn) rn dp * 1 result 15 0 or tp or ep * 2 1110sz rrr displacement with sign extension @(d:16,rn) 16 bits 1111sz rrr 15 0 23 15 0 rn dp * 1 result 15 0 or tp or ep * 2 4 register indirect 15 0 23 15 0 with pre-decrement rn dp * 1 result @?n or tp or ep *2 1011sz rrr register indirect 23 15 0 with post-increment dp * 1 rn @rn+ rn is incremented by +1 or +2 1100sz rrr after instruction execution. * 3 * 4 * 5 or tp or ep * 2 rn is decremented by ? or ? before instruction execution. * 3 * 4 * 5 1 or 2 displacement + + 47
table 3-8 effective address calculation (cont) no. addressing mode effective address calculation effective address 5 absolute address 23 15 0 @aa:8 h'00 br 0000sz101 ea extension data @aa:16 23 15 0 0001sz101 dp ea extension data 6 immediate operand is 1-byte ea #xx:8 extension data. 00000100 #xx:16 operand is 2-byte ea 00001100 extension data. 7 pc-relative 8 bits disp:8 15 0 23 15 0 no ea code pc cp * 1 result specified in op code 15 0 displacement with sign extension disp:16 16 bits 23 15 0 no ea code 15 0 cp * 1 result specified in op code pc 15 0 displacement ? ? 48
notes: * 1 the page register is ignored in minimum mode. * 2 the page register used in addressing modes 2, 3, and 4 depends on the general register : dp for r0, r1, r2, or r3; ep for r4 or r5; tp for r6 or r7. * 3 decrement by ? for a byte operand, and by ? for a word operand. * 4 the pre-decrement or post-increment is always 2 when r7 is specified, even if the operand is byte size. * 5 the drawing below shows what happens when the @-sp and @ sp+ addressing modes are used to save and restore the stack pointer. sp sp sp mov.w sp, @?p mov.w @sp+, sp old sp? (upper byte) old sp? (lower byte) 49
3.5 instruction set 3.5.1 overview the main features of the cpu instruction set are: ? a general-register architecture. ? orthogonality . addressing modes and data sizes can be specified independently in each instruction. ? 1.5 addressing modes (supporting register-register and register-memory operations) ? affinity for high-level languages, particularly c, with short formats for frequently-used instructions and addressing modes. the cpu instruction set includes 63 types of instructions, listed by function in table 3-9. table 3-9 instruction classification * bcc is a conditional branch instruction in which cc represents a condition code. tables 3-10 to 3-16 give a concise summary of the instructions in each functional category. the mov, add, and cmp instructions have special short formats, which are listed in table 3-17. for detailed descriptions of the instructions, refer to the h8/500 series programming manual . the notation used in tables 3-10 to 3-17 is defined below. function instructions types data transfer mov, ldm, stm, xch, swap, movtpe, movfpe 7 arithmetic operations add, sub, adds, subs, addx, subx, dadd, dsub, 17 mulxu, divxu, cmp, exts, extu, tst, neg, clr, tas logic operations and, or, xor, not 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, 8 rotxr bit manipulation bset, bclr, btst, bnot 4 branch bcc*, jmp, pjmp, bsr, jsr, pjsr, rts, prtd, 11 prts, rtd, scb (/f, /ne, /eq) system control trapa, trap/vs, rte, sleep, ldc, stc, andc, 12 orc, xorc, nop, link, unlk total 63 50
operation notation rd general register (destination) rs general register (source) rn general register (ead) destination operand (eas) source operand ccr condition code register n n (negative) bit of ccr z z (zero) bit of ccr v v (overflow) bit of ccr c c (carry) bit of ccr cr control register pc program counter cp code page register sp stack pointer fp frame pointer #imm immediate data disp displacement + addition subtraction multiplication division and logical or logical exclusive or logical move exchange not 51
3.5.2 data transfer instructions table 3-10 describes the seven data transfer instructions. table 3-10 data transfer instructions instruction size * function data mov (eas) (ead), #imm (ead) transfer mov:g b/w moves data between two general registers, or between mov:e b a general register and memory, or moves immediate data mov:i w to a general register or memory. mov:f b/w mov:l b/w mov:s b/w ldm w stack rn (register list) pops data from the stack to one or more registers. stm w rn (register list) stack pushes data from one or more registers onto the stack. xch w rs rd exchanges data between two general registers. swap b rd (upper byte) rd (lower byte) exchanges the upper and lower bytes in a general register . movtpe b rn (ead) transfers data from a general register to memory in synchronization with the e clock. movfpe b (eas) rd transfers data from memory to a general register in synchronization with the e clock. note: b?yte; w?ord 52
3.5.3 arithmetic instructions table 3-11 describes the 17 arithmetic instructions. table 3-11 arithmetic instructions instruction size function arithmetic add rd (eas) rd, (ead) #imm (ead) operations add:g b/w performs addition or subtraction on data in a general add:q b/w register and data in another general register or memory , or sub b/w on immediate data and data in a general register or memory . adds b/w subs b/w addx b/w rd (eas) c rd subx b/w performs addition or subtraction with carry or borrow on data in a general register and data in another general register or memory, or on immediate data and data in a general register or memory. dadd b (rd) 10 (rs) 10 c (rd) 10 dsub b performs decimal addition or subtraction on data in two general registers. mulxu b/w rd (eas) rd performs 8-bit 8-bit or 16-bit 16-bit unsigned multiplication on data in a general register and data in another general register or memory, or on data in a general register and immediate data. divxu b/w rd (eas) rd performs 16-bit 8-bit or 32-bit 16-bit unsigned division on data in a general register and data in another general register or memory, or on data in a general register and immediate data. cmp rn ?(eas), (ead) ?#imm cmp:g b/w compares data in a general register with data in another cmp:e b general register or memory, or with immediate data, or cmp:i w compares immediate data with data in memory. note: b?yte; w?ord 53
table 3-11 arithmetic instructions (cont) instruction size function arithmetic exts b ( of ) ( of ) operations converts byte data in a general register to word data by extending the sign bit. extu b 0 ( of ) converts byte data in a general register to word data by padding with zero bits. tst b/w (ead) ?0 compares general register or memory contents with 0. neg b/w 0 ?(ead) (ead) obtains the twos complement of general register or memory contents. clr b/w 0 (ead) clears general register or memory contents to 0. tas b (ead) ?0, (1) 2 ( of ) tests general register or memory contents, then sets the most significant bit (bit 7) to 1. note: b?yte; w?ord 3.5.4 logic operations table 3-12 lists the four instructions that perform logic operations. table 3-12 logic operation instructions instruction size function logical and b/w rd (eas) rd operations performs a logical and operation on a general register and another general register, memory, or immediate data. or b/w rd (eas) rd performs a logical or operation on a general register and another general register, memory, or immediate data. xor b/w rd (eas) rd performs a logical exclusive or operation on a general register and another general register, memory, or immediate data. not b/w (ead) (ead) obtains the ones complement of general register or memory contents. note: b?yte; w?ord 54
3.5.5 shift operations table 3-13 lists the eight shift instructions. table 3-13 shift instructions instruction size function shift shal b/w (ead) shift (ead) operations shar b/w performs an arithmetic shift operation on general register or memory contents. shll b/w (ead) shift (ead) shlr b/w performs a logical shift operation on general register or memory contents. rotl b/w (ead) shift (ead) rotr b/w rotates general register or memory contents. rotxl b/w (ead) rotate through carry (ead) rotxr b/w rotates general register or memory contents through the c (carry) bit. note: b?yte; w?ord 55
3.5.6 bit manipulations table 3-14 describes the four bit-manipulation instructions. table 3-14 bit-manipulation instructions instruction size function bit bset b/w ( of ) z, manipu- 1 ( of ) lations tests a specified bit in a general register or memory, then sets the bit to 1. the bit is specified by a bit number given in immediate data or a general register. bclr b/w ( of ) z, 0 ( of ) tests a specified bit in a general register or memory, then clears the bit to 0. the bit is specified by a bit number given in immediate data or a general register. bnot b/w ( of ) z, ( of ) tests a specified bit in a general register or memory, then inverts the bit. the bit is specified by a bit number given in immediate data or a general register. btst b/w ( of ) z tests a specified bit in a general register or memory. the bit is specified by a bit number given in immediate data or a general register. note: b?yte; w?ord 56
3.5.7 branching instructions table 3-15 describes the 11 branching instructions. table 3-15 branching instructions instruction size function branch bcc branches if condition cc is true. mnemonic description condition bra (bt) always (true) true brn (bf) never (false) false bhi high c z = 0 bls low or same c z = 1 bcc (bhs) carry clear c = 0 (high or same) bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp branches unconditionally to a specified address in the same page. pjmp branches unconditionally to a specified address in a specified page. bsr branches to a subroutine at a specified address in the same page. jsr branches to a subroutine at a specified address in the same page. pjsr branches to a subroutine at a specified address in a specified page. rts returns from a subroutine in the same page. 57
table 3-15 branching instructions (cont) instruction size function branch prts returns from a subroutine in a different page. rtd returns from a subroutine in the same page and adjusts the stack pointer. prtd returns from a subroutine in a different page and adjusts the stack pointer. scb/f controls a loop using a loop counter and/or a specified scb/ne termination condition. scb/eq 58
3.5.8 system control instructions table 3-16 describes the 12 system control instructions. table 3-16 system control instructions instruction size function system trapa generates a trap exception with a specified vector number . control trap/vs generates a trap exception if the v bit is set to 1 when the instruction is executed. rte returns from an exception-handling routine. link fp @?p; sp fp; sp + #imm sp creates a stack frame. unlk fp sp; @sp+ fp deallocates a stack frame created by the link instruction. sleep causes a transition to the power-down state. ldc b/w * (eas) cr moves immediate data or general register or memory contents to a specified control register. stc b/w * cr (ead) moves control register data to a specified general register or memory location. andc b/w * cr #imm cr logically ands a control register with immediate data. orc b/w * cr #imm cr logically ors a control register with immediate data. xorc b/w * cr #imm cr logically exclusive-ors a control register with immediate data. nop pc + 1 pc no operation. only increments the program counter. * the size depends on the control register. note on stack operation by ldc and stc instructions of h8/500 cpu when using the ldc and stc instructions to stack and unstack the br, ccr, tp, dp, and ep control registers in the h8/500 family, note the following point. h8/500 hardware does not permit byte access to the stack. if the ldc.b or stc.b assembler mnemonic is coded with the @r7 + (@sp+) or @?7 (@?p) addressing mode, the stack- pointer addressing mode takes precedence and hardware automatically performs word access. 59
specifically, the ldc.b and stc.b instructions are executed as follows. the following applies only to the stack-pointer addressing modes. in addressing modes that do not use the stack pointer, byte data access is performed as specified by the assembler mnemonic. (1) stc.b ep, @?p when word data access is applied to ep, both ep and dp are accessed. this instruction stores ep at address sp (old) ?, and dp at address sp (old) ?. (2) ldc.b @sp+, ep when word data access is applied to ep, both ep and dp are accessed. this instruction loads ep from address sp (old), and dp from address sp (old) +1, updating the dp value as well as the ep value. (3) stc.b ccr, @?p when word data access is applied to ccr, only ccr is accessed. this instruction stores identical ccr contents at both address sp (old) ? and address sp (old) ?. ep a dp b old sp ?2 before execution old sp ?1 old sp new sp after execution new sp + 1 new sp + 2 a b ep a dp b old sp after execution old sp + 1 old sp + 2 new sp ?2 before execution new sp ?1 new sp a b ep a dp b ccr a old sp ?2 before execution old sp ?1 old sp new sp after execution new sp + 1 new sp + 2 a b 60
(4) ldc.b @sp+, ccr when word data access is applied to ccr, only ccr is accessed. this instruction loads ccr from address sp (old) +1. note that the value in address sp (old) is not loaded. br, dp, and tp are accessed in the same way as ccr. when dp is specified, both ep and dp are accessed, but when ccr, br, dp, or tp is specified, only the specified register is accessed. ccr old sp after execution old sp + 1 old sp + 2 new sp ?2 before execution new sp ?1 new sp a b ccr b 61
3.5.9 short-format instructions the add, cmp, and mov instructions have special short formats. table 3-17 lists these short formats together with the equivalent general formats. the short formats are a byte shorter than the corresponding general formats, and most of them execute one state faster. table 3-17 short-format instructions and equivalent general formats short-format execution equivalent general- execution instruction length states * 2 format instruction length states * 2 add:q #xx,rd * 1 2 2 add:g #xx:8,rd 3 3 cmp:e #xx:8,rd 2 2 cmp:g.b #xx:8,rd 3 3 cmp:i #xx:16,rd 3 3 cmp:g.w #xx:16,rd 4 4 mov:e #xx:8,rd 2 2 mov:g.b #xx:8,rd 3 3 mov:i #xx:16,rd 3 3 mov:g.w #xx:16,rd 4 4 mov:l @aa:8,rd 2 5 mov:g @aa:8,rd 3 5 mov:s rs,@aa:8 2 5 mov:g rs,@aa:8 3 5 mov:f @(d:8,r6),rd 2 5 mov:g @(d:8,r6),rd 3 5 mov:f rs,@(d:8,r6) 2 5 mov:g rs,@(d:8,r6) 3 5 notes: * 1 the add:q instruction accepts other destination operands in addition to a general register, but the immediate data value (#xx) is limited to 1 or 2. * 2 number of execution states for access to on-chip memory. 3.6 operating modes the cpu operates in one of two modes: the minimum mode or the maximum mode. these modes are selected by the mode pins (md 2 to md 0 ). 3.6.1 minimum mode the minimum mode supports a maximum address space of 64 kbytes. the page registers are ignored. instructions that branch across page boundaries (pjmp, pjsr, prts, prtd) are invalid. 62
3.6.2 maximum mode in the maximum mode the page registers are valid, expanding the maximum address space to 1 mbyte. the address space is divided into 64-kbyte pages. the pages are separate; it is not possible to move continuously across a page boundary. it is possible to move from one page to another with branching instructions (pjmp, pjsr, prts, prtd). the trapa instruction and branches to interrupt-handling routines can also jump across page boundaries. it is not necessary for a program to be contained in a single 64-kbyte page. when data access crosses a page boundary, the program must rewrite the page register before it can access the data in the next page. for further information on the operating modes, see section 2, ?cu operating modes and address space. 3.7 basic operational timing 3.7.1 overview the cpu operates on a system clock (? which is created by dividing an oscillator frequency (fosc) by two. one period of the system clock is referred to as a ?tate.? the cpu accesses memory in a cycle consisting of 2 or 3 states. the cpu uses different methods to access on-chip memory, the on-chip register field, and external devices. access to on-chip memory (ram, rom): for maximum speed, access to on-chip memory (ram, rom) is performed in two states, using a 16-bit-wide data bus. figure 3-6 shows the on-chip memory access cycle. figure 3-7 indicates the pin states. the bus control output signals go to the nonactive state during the access. access to on-chip register field (addresses h'fe80 to h'ffff): the access cycle consists of three states. the data bus is 8 bits wide. figure 3-8 shows the on-chip supporting module access cycle. figure 3-9 indicates the pin states. 63
access to external devices: the access cycle consists of three states. the data bus is 8 bits wide. figure 3-10 (a) and (b) shows the external access cycle. additional wait states (tw) can be inserted by the wait-state controller (wsc). 3.7.2 on-chip memory access cycle t state memory cycle 1 t state 2 internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) figure 3-6 on-chip memory access timing 64
3.7.3 pin states during on-chip memory access t state 1 t state 2 a to a r/w (write access) 19 0 as, ds, rd, wr d to d 7 0 r/w (read access) ?igh high-impedance figure 3-7 pin states during access to on-chip memory 65
3.7.4 register field access cycle (addresses h'fe80 to h'ffff) t state memory cycle 1 t state 2 t state 3 address read data internal address bus internal read signal internal write signal internal data bus (write access) internal data bus (read access) write data figure 3-8 register field access timing 66
3.7.5 pin states during register field access (addresses h'fe80 to h'ffff) t state 1 t state 2 t state 3 ?igh a to a r/w (read access) 19 0 as, ds, rd, wr d to d 7 0 r/w (write access) high-impedance figure 3-9 pin states during register field access 67
3.7.6 external access cycle read cycle t state 1 t state 2 t state 3 address r/w d ? 7 0 a ? 19 0 as wr ds rd ?igh read data figure 3-10 (a) external access cycle (read access) 68
3.8 cpu states 3.8.1 overview the cpu has five states: the program execution state, exception-handling state, bus-released state, reset state, and power-down state. the power-down state is further divided into the sleep mode, software standby mode, and hardware standby mode. figure 3-11 summarizes these states, and figure 3-12 shows a map of the state transitions. write cycle t state 1 t state 2 t state 3 address write data ?igh r/w d ? 7 0 a ? 19 0 as wr ds rd figure 3-10 (b) external access cycle (write access) 69
state program execution state exception-handling state bus-released state reset state power-down state the cpu executes program instructions in sequence. a transient state in which the cpu executes a hardware sequence (saving the program counter and status register, fetching a vector from the vector table, etc.) triggered by a reset, interrupt, or other exception. the state in which the cpu has released the external bus in response to a bus request signal from an external device, and is waiting for the bus to be returned. the state in which the cpu and all on-chip supporting modules have been initialized and are stopped. a state in which some or all of the clock signals are stopped to conserve power. sleep mode software standby mode hardware standby mode figure 3-11 operating states 70
3.8.2 program execution state in this state the cpu executes program instructions in normal sequence. 3.8.3 exception-handling state the exception-handling state is a transient state that occurs when the cpu alters the normal program flow due to an interrupt, trap instruction, address error, or other exception. in this state the cpu carries out a hardware-controlled sequence that prepares it to execute a user-coded exception-handling routine. breq = 0 breq = 0 breq = 1 bus-released state end of exception handling request for exception handling sleep instruction with standby flag set sleep instruction interrupt request nmi program execution state exception-handling state sleep mode software standby mode hardware standby mode reset state * stby = 1, res = 0 * from any state except the hardware standby mode, a transition to the reset state occurs whenever res goes low. * a transition to the hardware standby mode from any state occurs when stby goes low. breq = 1 res = 1 1 * 2 1 2 figure 3-12 state transitions 71
in the hardware exception-handling sequence the cpu does the following: 1. saves the program counter and status register (in minimum mode) or program counter, code page register, and status register (in maximum mode) to the stack. 2. clears the t bit in the status register to 0. 3. fetches the start address of the exception-handling routine from the exception vector table. 4. branches to that address, returning to the program execution state. see section 4, ?xception handling,?for further information on the exception-handling state. 3.8.4 bus-released state when so requested, the cpu can grant control of the external bus to an external device. while an external device has the bus right, the cpu is said to be in the bus-released state. the bus right is controlled by two pins: ? breq: input pin for the bus request signal from an external device ? back: output pin for the bus request acknowledge signal from the cpu, indicating that the cpu has released the bus the procedure by which the cpu enters and leaves the bus-released state is: 1. the cpu receives a low breq signal from an external device. 2. the cpu places the address bus pins (a 19 ?a 0 ), data bus pins (d 7 ?d 0 ) and bus control pins (rd, wr, r/w, ds, and as) in the high-impedance state, sets the back pin to the low level to indicate that it has released the bus, then halts. 3. the external device that requested the bus (with the breq signal) becomes the bus master. it can use the data bus and address bus. the external device is responsible for manipulating the bus control signals (rd, wr, r/w, ds, and as). 4. when the external device finishes using the bus, it clears the breq signal to the high level. the cpu then reassumes control of the bus and returns to the program execution state. bus release timing: the cpu can release the bus right at the following times: 1. the breq signal is sampled during every memory access cycle (instruction prefetch or data read/write). if breq is low, the cpu releases the bus right at the end of the cycle. (in word data access to external memory or an address from h'fe80 to h'ffff, the cpu does not release the bus right until it has accessed both the upper and lower data bytes.) 2. during execution of the mulxu and divxu instructions, since considerable time may pass without an instruction prefetch or data read/write, breq is also sampled at internal machine cycles, and the bus right is released if breq is low. 3. the bus right can also be released in the sleep mode. the cpu does not recognize interrupts while the bus is released. 72
timing charts: timing charts of the operation by which the bus is released are shown in figure 3-13 for the case of bus release during an on-chip memory read cycle, in figure 3-14 for bus release during an external memory read cycle, and in figure 3-15 for bus release while the cpu is performing an internal operation. rd, wr, r/w ds, as d ? 7 0 a ? 19 0 breq back on-chip memory access cycle bus-right release cycle cpu cycle t 2 t 1 t 2 t x t x t x t x t 1 * * * (1) (2) (3) (4) (5) fig. 3-13 (1) the breq pin is sampled at the start of the t 1 state and the low level is detected. (2) at the end of the memory access cycle, the back pin goes low and the cpu releases the bus. (3) while the bus is released, the breq pin is sampled at each tx state. (4) a high level is detected at the breq pin. (5) the back pin is returned to the high level, ending the bus-right release cycle. * t 1 and t 2 : on-chip memory access states. tx : bus-right released state. figure 3-13 bus-right release cycle (during on-chip memory access cycle) 73
rd, wr r/w, ds d ed 7 0 a ea 19 0 ? breq back (1) (2) (3) (4) fig. 3-14 bus-right release cycle cpu cycle external access cycle t 1 t 2 t w t x t 3 t x t x t 1 * * (1) the breq pin is sampled at the start of the t w state and the low level is detected. (2) at the end of the external access cycle, the back pin goes low and the cpu releases the bus. (3) the breq pin is sampled at the t x state and a high level is detected. (4) the back pin is returned to the high level, ending the bus-right release cycle. * t w : wait state. t x : bus-right released state. figure 3-14 bus-right release cycle (during external access cycle) 74
rd, wr r/w, ds d ed 7 0 a ea 19 0 ? breq back bus-right release cycle cpu cycle cpu internal operation t i t i t i t x t x t 1 * * t x t i (1) (2) (3) (4) (1) the breq pin is sampled at the start of a t i state and the low level is detected. (2) at the end of the internal operation cycle, the back pin goes low and the cpu releases the bus. (3) the breq pin is sampled at the t x state and a high level is detected. (4) the back pin is returned to the high level, ending the bus-right release cycle. * t i : internal cpu operation state. t x : bus-right released state. figure 3-15 bus-right release cycle (during internal cpu operation) 75
notes: the breq signal must be held low until back goes low. if breq returns to the high level before back goes low, the bus release operation may be executed incorrectly. to leave the bus-released state, the high level at the breq pin must be sampled two times. if breq returns to low before it is sampled two times, the bus released cycle will not end. the bus release operation is enabled only when the brle bit in the port 1 control register (p1cr) is set to 1. when this bit is cleared to 0 (its initial value), the breq and back pins are used for general-purpose input and output, as p1 3 and p1 2 . an instruction that sets the brle bit is: bset.b #3, @h'fefc note the following point when using the bus release function. if the breq signal is asserted and an interrupt is requested simultaneously during execution of the sleep instruction, the back signal may fail to be output even though the cpu has released the bus. this may cause the system to stop for the interval during which breq is asserted, with no device in control of the bus. the interrupts that can cause this state include nmi, irq, and all the interrupts from on-chip supporting modules. when the breq signal is deasserted, ending this state, the cpu takes control of the bus again and resumes normal instruction execution. the following methods can be used to avoid entering this state. method 1: if the breq signal is used, do not use the sleep instruction. method 2: disable the breq signal during execution of the sleep instruction. this can be done by clearing the bus release enable bit (brle) in the port 1 control register (p1cr) to 0 immediately before executing the sleep instruction. (when the brle bit is cleared, low inputs on the breq line are not latched on-chip.) place instructions to set the brle bit to 1 at the beginning of interrupt-handling routines. if the data transfer controller (dtc) is used, place an instruction to set the brle bit immediately after the sleep instruction. if method 2 is used, breq inputs will be ignored while the chip is in sleep mode. (coding example) main program interrupt-handling routine bset.b #3, @syscr1 bclr.b #3, @syscr1 sleep bset.b #3, @syscr1 rte 76
3.8.5 reset state in the reset state, the cpu and all on-chip supporting modules are initialized and placed in the stopped state. the cpu enters the reset state whenever the res pin goes low, unless the cpu is currently in the hardware standby mode. it remains in the reset state until the res pin goes high. see section 4.2, ?eset,?for further information on the reset state. 3.8.6 power-down state the power-down state comprises three modes: the sleep mode, the software standby mode, and the hardware standby mode. see section 18, ?ower-down state,?for further information. 77
3.9 programming notes 3.9.1 restriction on address location the following restriction applies when instructions are located in on-chip ram. restriction instruction execution cannot proceed continuously from an external address to on-chip ram. solution to execute instructions located in on-chip ram, use a branch instruction (examples: bcc, jmp, etc.) to branch to the first instruction located in on-chip ram. do not place instruction code in the last three bytes of external memory (h'f67d to h'f67f). h'f67a h'f67b h'f67c h'f67d h'f67e h'f67f h'f680 h'f681 nop nop nop nop nop nop nop nop nop bra disp nop nop not executable do not place instruction code here branch h'f67a h'f67b h'f67c h'f67d h'f67e h'f67f h'f680 h'f681 execution disabled execution enabled 78
section 4 exception handling 4.1 overview 4.1.1 types of exception handling and their priority as indicated in table 4-1 (a) and (b), exception handling can be initiated by a reset, address error, trace, interrupt, or instruction. an instruction initiates exception handling if the instruction is an invalid instruction, a trap instruction, or a divxu instruction with zero divisor. exception handling begins with a hardware exception-handling sequence which prepares for the execution of a user-coded software exception-handling routine. there is a priority order among the different types of exceptions, as shown in table 4-1 (a). if two or more exceptions occur simultaneously, they are handled in their order of priority. an instruction exception cannot occur simultaneously with other types of exceptions. table 4-1 (a) exceptions and their priority exception start of exception- priority type source detection timing handling sequence high reset external, res low-to-high transition immediately internal address error internal instruction fetch or data end of instruction execution read/write bus cycle trace internal end of instruction execution, end of instruction execution if t = 1 in status register interrupt external, end of instruction execution or end of instruction execution internal end of exception-handling low sequence table 4-1 (b) instruction exceptions exception type start of exception-handling sequence invalid instruction attempted execution of instruction with undefined code trap instruction started by execution of trap instruction zero divide attempted execution of divxu instruction with zero divisor 79
4.1.2 hardware exception-handling sequence the hardware exception-handling sequence varies depending on the type of exception. when exception handling is initiated by a factor other than a reset, the cpu: 1. saves the program counter and status register (in minimum mode) or program counter, code page register, and status register (in maximum mode) to the stack. 2. clears the t bit in the status register to 0. 3. fetches the start address of the exception-handling routine from the exception vector table. 4. branches to that address. for an interrupt, the cpu also alters the interrupt mask level in bits i2 to i0 of the status register. for a reset, step 1 is omitted. see section 4.2, ?eset? for the full reset sequence. 4.1.3 exception factors and vector table the factors that initiate exception handling can be classified as shown in figure 4-1. the starting addresses of the exception-handling routines for each factor are contained in an exception vector table located in the low addresses of page 0. the vector addresses are listed in table 4-2. note that there are different addresses for the minimum and maximum modes. 80
exception ?reset ?interrupt ?address error ?instruction ?trace external interrupt internal interrupt invalid instruction zero divide trapa instruction trap/vs instruction nmi irq 0 irq 1 to irq 5 internal interrupt requested by on- chip module figure 4-1 types of factors causing exception handling 81
table 4-2 exception vector table vector address type of exception minimum mode maximum mode * 1 reset (initialize pc) h'0000 to h'0001 h'0000 to h'0003 ? (reserved for system) h'0002 to h'0003 h'0004 to h'0007 invalid instruction h'0004 to h'0005 h'0008 to h'000b divxu instruction (zero divide) h'0006 to h'0007 h'000c to h'000f trap/vs instruction h'0008 to h'0009 h'0010 to h'0013 h'000a to h'000b h'0014 to h'0017 ? (reserved for system) to to h'000e to h'000f h'001c to h'001f address error h'0010 to h'0011 h'0020 to h'0023 trace h'0012 to h'0013 h'0024 to h'0027 ? (reserved for system) h'0014 to h'0015 h'0028 to h'002b nonmaskable external interrupt (nmi) h'0016 to h'0017 h'002c to h'002f h'0018 to h'0019 h'0030 to h'0033 ? (reserved for system) to to h'001e to h'001f h'003c to h'003f trapa instruction (16 vectors) h'0020 to h'0021 h'0040 to h'0043 to to h'003e to h'003f h'007c to h'007f external interrupts irq 0 h'0040 to h'0041 h'0080 to h'0083 irq 1 h'0048 to h'0049 h'0090 to h'0093 irq 2 h'0050 to h'0051 h'00a0 to h'00a3 irq 3 h'0052 to h'0053 h'00a4 to h'00a7 irq 4 h'0058 to h'0059 h'00b0 to h'00b3 irq 5 h'005a to h'005b h'00b4 to h'00b7 internal interrupts * 2 h'0060 to h'0061 h'00c0 to h'00c3 to to h'0098 to h'0099 h'0130 to h'0133 notes: * 1. the exception vector table is located at the beginning of page 0. * 2. for details of the internal interrupt vectors, see table 5-2. 82
4.2 reset 4.2.1 overview a reset has the highest exception-handling priority. when the res pin goes low, all current processing is halted and the h8/534 or h8/536 chip enters the reset state. a reset initializes the internal status of the cpu and the registers of the on-chip supporting modules and i/o ports. it does not initialize the on-chip ram. when the res pin returns from low to high, the chip comes out of the reset state and begins executing the hardware reset sequence. 4.2.2 reset sequence the reset signal is detected when the res pin goes low. to ensure that the h8/534 or h8/536 is reset, the res pin should be held low for at least 20 ms at power-up. to reset the h8/534 or h8/536 during operation, the res pin should be held low for at least 6 system clock cycles. see table d-1, ?tatus of ports?in appendix d for the status of other pins in the reset state. when the res pin returns to the high state after being held low for the necessary time, the hardware reset exception-handling sequence begins, during which: 1. in the status register (sr), the t bit is cleared to disable the trace mode, and the interrupt mask level (bits i2 to i0) is set to 7. a reset disables all interrupts, including nmi. 2. the cpu loads the reset start address from the vector table into the program counter and begins executing the program at that address. the contents of the vector table differs between minimum mode and maximum mode as indicated in figure 4-2. this affects step 3 as follows: minimum mode: one word is copied from addresses h'0000 and h'0001 in the vector table to the program counter. program execution then begins from the address in the program counter (pc). 83
maximum mode: two words are read from addresses h'0000 to h'0003 in the vector table. the byte in address h'0000 is ignored. the byte in address h'0001 is copied to the code page register (cp). the contents of addresses h'0002 and h'0003 are copied to the program counter. program execution starts from the address indicated by the code page register and program counter. figure 4-3 shows the timing of the reset sequence in minimum mode. figure 4-4 shows the timing of the reset sequence in maximum mode. 4.2.3 stack pointer initialization the hardware reset sequence does not initialize the stack pointer, so this must be done by software. if an interrupt were to be accepted after a reset and before the stack pointer (sp) is initialized, the program counter and status register would not be saved correctly, causing a program crash. this danger can be avoided by coding the reset routine as explained next. when the chip comes out of the reset state all interrupts, including nmi, are disabled, so the instruction at the reset start address is always executed. in the minimum mode, this instruction should initialize the stack pointer (sp). in the maximum mode, this instruction should be an ldc instruction initializing the stack page register (tp), and the next instruction should initialize the stack pointer. execution of the ldc instruction disables interrupts again, ensuring that the stack pointer initializing instruction is executed. h?000 pc (upper) h?001 pc (lower) (1) minimum mode h?000 don? care h?001 cp (2) maximum mode h?002 pc (upper) h?003 pc (lower) fig. 4-2 figure 4-2 reset vector 84
res internal address bus internal data bus (16 bits) internal read signal internal write signal (1) (2) vector address (3) instruction execution cycle prefetch first instruction of program reset vector internal processing cycle minimum 6 states (1) instruction prefetch address (2) operation code (3) program start address (4) first instruction of program note: this timing chart applies to the minimum mode when the program and stack areas are both in on-chip memory and the program starts at an even address. vector (4) figure 4-3 reset sequence (minimum mode, on-chip memory) 85
(1) vector address vector address + 1 vector address + 2 vector address + 3 (2) internal processing cycle note: this diagram applies to maximum mode when the program area and vector table are both in external memory. after a reset, the wait-state controller inserts three wait states in each bus cycle. (1) program start address (2) first instruction of program reset vector prefetch first instruction of program instruction execution cycle res rd lwr, hwr d to d 15 0 a to a 23 0 don? care vector cp vector pc vector pc h l read signal write signal figure 4-4 reset sequence (maximum mode, external memory) 86
4.3 address error there are three causes of address errors: ? illegal instruction prefetch ? word data access at odd address ? off-chip access in single-chip mode an address error initiates the address error exception-handling sequence. this sequence clears the t bit of the status register to 0 to disable the trace mode, but does not affect the interrupt mask level in bits i2 to i0. 4.3.1 illegal instruction prefetch an attempt to prefetch an instruction from the register field in memory addresses h'fe80 to h'ffff causes an address error regardless of the mcu operating mode. handling of this address error begins when the prefetch cycle that caused the error has been completed and execution of the current instruction has also been completed. the program counter value pushed on the stack is the address of the instruction immediately following the last instruction executed. program code should not be located in addresses h'fe7d to h'fe7f. if the cpu executes an instruction in these addresses, it will attempt to prefetch the next instruction from the register field, causing an address error. 4.3.2 word data access at odd address if an attempt is made to access word data starting at an odd address, an address error occurs regardless of the mcu operating mode. the program counter value pushed on the stack in the handling of this error is the address of the next instruction (or next but one) after the instruction that attempted the illegal word access. 4.3.3 off-chip address access in single-chip mode in the single-chip mode there is no external memory, so in addition to the address errors described above, the following two types of address errors can occur. access to addresses h'8000 to h'f67f(h8/534): these addresses exist neither in on-chip rom or ram nor in the on-chip register field, so an address error occurs if they are accessed for any purpose: for instruction prefetch, byte data access, or word data access. program code should not be located in the last three bytes of on-chip rom (addresses h'7ffd to 87
h'7fff). if the cpu excutes an instruction in these addresses, it will attempt to prefetch the next instruction from addresses h'8000 to h'8002, causing an address error. access to disabled ram area: the on-chip ram area (h'f680 to h'fe7f) can be disabled by clearing the rame bit in the ram control register (ramcr). if any form of ram access is attempted in this state in the single-chip mode, an address error occurs. 4.4 trace when the t bit of the status register is set to 1, the cpu operates in trace mode. a trace exception occurs at the completion of each instruction. the trace mode can be used to execute a program for debugging by a debugger. in the trace exception sequence the t bit of the status register is cleared to 0 to disable the trace mode while the trace routine is executing. the interrupt mask level in bits i2 to i0 is not changed. interrupts are accepted as usual during the trace routine. in the status-register data saved on the stack, the t bit is set to 1. when the trace routine returns with the rte instruction, the status register is popped from the stack and the trace mode resumes. if an address error occurs during execution of the first instruction after the return from the trace routine, since the address error has higher priority, the address error exception-handling sequence is initiated, clearing the t bit in the status register to 0 and making it impossible to trace this instruction. 4.5 interrupts interrupts can be requested from seven external sources (nmi, irq 0 , and irq 1 to irq 5 ) and eight on-chip supporting modules: the 16-bit free-running timers (frt1 to frt3), the 8-bit timer, the serial communication interfaces (sci1 and sci2), the a/d converter, and the watchdog timer (wdt). the on-chip interrupt sources can request a total of nineteen different types of interrupts, each having its own interrupt vector. figure 4-5 lists the interrupt sources and the number of different interrupts from each source. each interrupt source has a priority. nmi interrupts have the highest priority, and are normally accepted unconditionally. the priorities of the other interrupt sources are set in control registers (ipr a to d) in the register field at the high end of page 0 and can be changed by software. priority levels range from 0 (low) to 7 (high), with nmi considered to be on level 8. irq 0 and irq 1 can be prioritized individually. irq 2 and irq 3 are prioritized as a pair. irq 4 and irq 5 are also prioritized as a pair. the on-chip supporting modules are prioritized as modules. 88
the on-chip interrupt controller decides whether an interrupt can be accepted by comparing its priority with the interrupt mask level, and determines the order in which to accept competing interrupt requests. interrupts that are not accepted immediately remain pending until they can be accepted later. when it accepts an interrupt, the interrupt controller also decides whether to interrupt the cpu or start the on-chip data transfer controller (dtc). this decision is controlled by bits set in four data transfer enable registers (dtea to dtef) in the register field. the dtc is started if the corresponding bit in dtea to dtef is set to 1; otherwise a cpu interrupt is generated. dtc interrupts provide an efficient way to send and receive blocks of data via the serial communication interface, or to transfer data between memory and i/o without detailed cpu programming. the cpu stops while the dtc is operating. dtc interrupts are described in section 6, ?ata transfer controller. the hardware exception-handling sequence for a cpu interrupt clears the t bit in the status register to 0 and sets the interrupt mask level in bits i2 to i0 to the level of the interrupt it has accepted. this prevents the interrupt-handling routine from being interrupted except by a higher -level interrupt. the previous interrupt mask level is restored on the return from the interrupt-handling routine. for further information on interrupts, see section 5, ?nterrupt controller. 89
interrupt sources internal interrupts nmi (1) irq 0 (1) irq 1 to irq 5 (5) 16-bit frt1 (4) 16-bit frt2 (4) 16-bit frt3 (4) 8-bit timer (3) sci (3) a/d converter (1) wdt * (1) nmi: nonmaskable interrupt irq: interrupt request frt: free-running timer sci: serial communication interface wdt: watchdog timer * when the watchdog timer is used in interval timer mode, and interrupt is requested at each counter overflow. external interrupts figure 4-5 interrupt sources (and number of interrupt types) 90
4.6 invalid instruction an invalid instruction exception occurs if an attempt is made to execute an instruction with an undefined operation code or illegal addressing mode specification. the program counter value pushed on the stack is the value of the program counter when the invalid instruction code was detected. in the invalid instruction exception-handling sequence the t bit of the status register is cleared to 0, but the interrupt mask level (i2 to i0) is not affected. 4.7 trap instructions and zero divide a trap exception occurs when the trapa or trap/vs instruction is executed. a zero divide exception occurs if an attempt is made to execute a divxu instruction with a zero divisor. in the exception-handling sequences for these exceptions the t bit of the status register is cleared to 0, but the interrupt mask level (i2 to i0) is not affected. if a normal interrupt is requested while a trap or zero-divide instruction is being executed, after the trap or zero-divide exception-handling sequence, the normal interrupt exception-handling sequence is carried out. trapa instruction: the trapa instruction always causes a trap exception. the trapa instruction includes a vector number from 0 to 15, allowing the user to provide up to sixteen different trap-handling routines. trap/vs instruction: when the trap/vs instruction is executed, a trap exception occurs if the overflow (v) bit in the condition code register is set to 1. if the v bit is cleared to 0, no exception occurs and the next instruction is executed. divxu instruction with zero divisor: an exception occurs if an attempt is made to divide by zero in a divxu instruction. 4.8 cases in which exception handling is deferred in the cases described next, the address error exception, trace exception, external interrupt (nmi, irq 0 , and irq 1 to irq 5 ) requests, and internal interrupt requests (23 types) are not accepted immediately but are deferred until after the next instruction has been executed. 4.8.1 instructions that disable interrupts interrupts are disabled immediately after the execution of five instructions: xorc, orc, andc, ldc, and rte. suppose that an internal interrupt is requested and the interrupt controller, after checking the interrupt priority and interrupt mask level, notifies the cpu of the interrupt, but the cpu is 91
currently executing one of the five instructions listed above. after executing this instruction the cpu always proceeds to the next instruction. (and if the next instruction is one of these five, the cpu also proceeds to the next instruction after that.) the exception-handling sequence starts after the next instruction that is not one of these five has been executed. the following is an example: (example) 4.8.2 disabling of exceptions immediately after a reset if an interrupt is accepted after a reset and before the stack pointer (sp) is initialized, the program counter and status register will not be saved correctly, leading to a program crash. to prevent this, when the chip comes out of the reset state all interrupts, including the nmi, are disabled, so the first instruction of the reset routine is always executed. as noted earlier, in the minimum mode, this instruction should initialize the stack pointer (sp). in the maximum mode, the first instruction should be an ldc instruction that initializes the stack page register (tp); the next instruction should initialize the stack pointer. 4.8.3 disabling of interrupts after a data transfer cycle if an interrupt starts the data transfer controller and another interrupt is requested during the data transfer cycle, when the data transfer cycle ends, the cpu always executes the next instruction before handling the second interrupt. even if a nonmaskable interrupt (nmi) occurs during a data transfer cycle, it is not accepted until the next instruction has been executed. an example of this is shown below. ldc.b #h'00,tp mov.b #h'00,@wcr program flow interrupt controller notifies cpu of interrupt to exception-handling sequence mov.w #h'fe80,sp cpu executes the instruction next to ldc before starting exception handling . . . . . . . . . 92
4.9 stack status after completion of exception handling the status of the stack after an exception-handling sequence is described below. table 4-3 shows the stack after completion of the exception-handling sequence for various types of exceptions in the minimum and maximum modes. table 4-3 stack after exception handling sequence note: the rte instruction returns to the next instruction after the instruction being executed when the exception occurred. dtc interrupt request mov.w r0,@h'fe00 program flow to nmi exception-handling sequence nmi interrupt after data transfer cycle, cpu executes next instruction before branching to exception handling add.w r2,r0 mov.w #h'fe02,r0 data transfer cycle (example) . . . . . . . . exception factor minimum mode maximum mode trace interrupt trap zero divide (divxu) sp table 4-3 sr (upper byte) tp:sp sr (upper byte) sr (lower byte) sr (lower byte) next instruction address (upper byte) don?-care next instruction address (lower byte) next instruction page (8 bits) next instruction address (upper byte) next instruction address (lower byte) 93
table 4-3 stack after exception handling sequence (cont) note: the program counter value pushed on the stack is not necessarily the address of the first byte of the invalid instruction. note: the program counter value pushed on the stack is the address of the next instruction after the last instruction successfully executed. exception factor minimum mode maximum mode invalid instruction sp table 4-3(cont) sr (upper byte) tp:sp sr (upper byte) sr (lower byte) sr (lower byte) pc when error occurred (upper byte) don?-care pc when error occurred (lower byte) cp when error occurred (8 bits) pc when error occurred (upper byte) pc when error occurred (lower byte) address error sp table 4-3(cont) sr (upper byte) tp:sp sr (upper byte) sr (lower byte) sr (lower byte) pc when error occurred (upper byte) don?-care pc when error occurred (lower byte) cp when error occurred (8 bits) pc when error occurred (upper byte) pc when error occurred (lower byte) 94
4.9.1 pc value pushed on stack for trace, interrupts, trap instructions, and zero divide exceptions the program counter value pushed on the stack for a trace, interrupt, trap, or zero divide exception is the address of the next instruction at the time when the interrupt was accepted. the rte instruction accordingly returns to the next instruction after the instruction executed before the exception-handling sequence. 4.9.2 pc value pushed on stack for address error and invalid instruction exceptions the program counter value pushed on the stack for an address error or invalid instruction exception differs depending on the conditions when the exception occurred. 4.10 notes on use of the stack if the stack pointer is set to an odd address, an address error will occur when the stack is accessed during interrupt handling or for a subroutine call. the stack pointer should always point to an even address. to keep the stack pointer pointing to an even address, a program should use word data size when saving or restoring registers to and from the stack. in the @?p or @sp+ addressing mode, the cpu performs word access even if the instruction specifies byte size. (this is not true in the @?n and @rn+ addressing modes when rn is a register from r0 to r6.) 95
section 5 interrupt controller 5.1 overview the interrupt controller decides which interrupts to accept, and how to deal with multiple interrupts. it also decides whether an interrupt should be served by the cpu or by the data transfer controller (dtc). this section explains the features of the interrupt controller, describes its internal structure and control registers, and details the handling of interrupts. for detailed information on the data transfer controller, see section 6, ?ata transfer controller. 5.1.1 features three main features of the interrupt controller are: interrupt priorities are user-programmable. user programs can set priority levels from 7 (high) to 0 (low) in six interrupt priority (ipr) registers for irq 0 , irq 1 to irq 5 , and each of the on-chip supporting modules?or every interrupt, that is, except the nonmaskable interrupt (nmi). nmi has the highest priority level (8) and is normally always accepted. an interrupt with priority level 0 is always masked. multiple interrupts on the same level are served in a default priority order. lower-priority interrupts remain pending until higher-priority interrupts have been handled. for most interrupts, software can select whether to have the interrupt served by the cpu or the on-chip data transfer controller (dtc). user programs can make this selection by setting and clearing bits in four data transfer enable (dte) registers. the data transfer controller can be started by any interrupts except nmi, the error interrupt (eri) from the on-chip serial communication interface, and the overflow interrupts (fovi and ovi) from the on-chip timers. 97
5.1.2 block diagram figure 5-1 shows the block configuration of the interrupt controller. irq nmi frt1 frt2 frt3 8 bit timer sci a/d converter interrupt request signals from modules interrupt controller nmi request interrupt request dtc request com- parator dtea to dtef 2 sr (cpu) frt: sci: sr: ipra to iprf: dtea to dtef: 16 bits free running timer serial communication interface status register interrupt priority register data transfer enable register irq /interval timer 0 1 irq /irq 2 3 irq /irq 4 5 priority decision ipra to iprf i 1 i 0 i figure 5-1 interrupt controller block diagram 98
5.1.3 register configuration the six interrupt priority registers (ipra to iprf) and six data transfer enable registers (dtea to dtef) are 8-bit registers located at addresses h'ff00 to h'ff0d in the register field in page 0 of the address space. table 5-1 lists their attributes. table 5-1 interrupt controller registers see section 6.2.5, ?ata transfer enable registers a to f?for further information about dtea to dtef. 5.2 interrupt types there are 30 distinct types of interrupts: 7 external interrupts originating off-chip and 23 internal interrupts originating in the on-chip supporting modules. 5.2.1 external interrupts the seven external interrupts are nmi, irq 0 , and irq 1 to irq 5 . nmi (nonmaskable interrupt): this interrupt has the highest priority level (8) and cannot be masked. an nmi is generated by input to the nmi pin, and can also be generated by a watchdog timer (wdt) overflow. the input at the nmi pin is edge-sensed. a user program can select whether to have the interrupt occur on the rising edge or falling edge of the nmi input by setting or clearing the nonmaskable interrupt edge bit (nmieg) in system control register 1 (syscr1). in the nmi exception-handling sequence, the t (trace) bit in the cpu status register (sr) is cleared to "0," and the interrupt mask level in i2 to i0 is set to 7, masking all other interrupts. the interrupt controller holds the nmi request until the nmi exception-handling sequence begins, name abbreviation read/write address initial value interrupt a ipra r/w h'ff00 h'00 priority b iprb r/w h'ff01 h'00 register c iprc r/w h'ff02 h'00 d iprd r/w h'ff03 h'00 e ipre r/w h'ff04 h'00 f iprf r/w h'ff05 h'00 data transfer a dtea r/w h'ff08 h'00 enable b dteb r/w h'ff09 h'00 register c dtec r/w h'ff0a h'00 d dted r/w h'ff0b h'00 e dtee r/w h'ff0c h'00 f dtef r/w h'ff0d h'00 99
then clears the nmi request, so if another interrupt is requested at the nmi pin during the nmi exception-handling sequence, the nmi exception-handling sequence will be carried out again. coding examples: to select the rising edge of the nmi input: bset.b #4, @h'fefc to select the falling edge of the nmi input: bclr.b #4, @h'fefc irq0 (interrupt request 0): an irq 0 interrupt can be requested by a low input to the irq 0 pin. a low irq 0 input requests an irq 0 interrupt if the interrupt request enable 0 bit (irq 0 e) in syscr1 is set to 1. irq 0 must be held low until the cpu accepts the interrupt. otherwise the request will be ignored. the irq 0 interrupt can be assigned any priority level from 7 to 0 by setting the corresponding value in the upper four bits of ipra. if bit 4 of data transfer enable register a (dtea) is set to 1, an irq 0 interrupt starts the data transfer controller. otherwise the interrupt is served by the cpu. in the cpu interrupt-handling sequence for irq 0 , the t bit of the status register is cleared to 0, and the interrupt mask level is set to the value in the upper four bits of ipra. coding examples: to enable irq 0 to be requested by irq 0 input: bset.b #5, @h'fefc to assign priority level 7 to irq 0 : or.b #70, @h'ff00 to have irq 0 start the dtc: bset.b #4, @h'ff08 irq 1 to irq 5 (interrupt request 1 to 5): an irq 1 to irq 5 interrupt is requested by a high-to- low transition at the irq 1 to irq 5 pin. the irq 1 interrupt is enabled only when the interrupt request enable 1 bit (irq 1 e) in syscr1 is set to 1. irq 2 to irq 5 are controlled by bits irq 2 e to irq 5 e in syscr2. (see section 9.7, ?ort 6.? interrupts irq 1 to irq 5 can be assigned any priority level from 7 (high) to 0 (low) by setting the corresponding value in ipra and iprb. the lower four bits of ipra determine the priority of irq 1 . the upper four bits of iprb determine the priority of irq 2 and irq 3 . the lower four bits of iprb determine the priority of irq 4 and irq 5 . interrupt requests irq 1 to irq 5 are held in the interrupt controller and cleared during the corresponding interrupt exception-handling sequence. contention among irq 1 to irq 5 is resolved when the cpu accepts the interrupt by taking the interrupt with the highest priority first and holding lower-priority interrupts pending. (contention between irq 2 and irq 3 , or between irq 4 and irq 5 , is resolved by the priority order shown in table 5-2.) 100
during the interrupt-handling routine, if the same external interrupt is requested again the request is held, but the exception-handling sequence is not carried out immediately because the interrupt is masked by bits i2 to i0 in the status register. on return from the interrupt-handling routine one more instruction is executed, then the pending exception-handling sequence is carried out. interrupts irq 1 to irq 5 are served by the cpu or dtc depending on dtea bit 0 and dteb bits 0, 1, 4, and 5. in the cpu interrupt exception-handling sequence for irq 1 to irq 5 , the t bit of the cpu status register is cleared to 0, and the interrupt mask level is set to the value in ipra or iprb. coding examples: to enable irq 1 to be requested by irq 1 input: bset.b #6, @h'fefc to assign priority level 7 to irq 0 and level 5 to irq 1 : mov.b #75, @h'ff00 to have irq 1 start the dtc: bset.b #0, @h'ff08 5.2.2 internal interrupts twenty-three types of internal interrupts can be requested by the on-chip supporting modules. each interrupt is separately vectored in the exception vector table, so it is not necessary for the user-coded interrupt handler routine to determine which type of interrupt has occurred. each of the internal interrupts can be enabled or disabled by setting or clearing an enable bit in the control register of the on-chip supporting module. an interrupt priority level from 7 to 0 can be assigned to each on-chip supporting module by setting interrupt priority registers c to f. within each module, different interrupts have a fixed priority order. for most of these interrupts, values set in data transfer enable registers c to f can select whether to have the interrupt served by the cpu or the data transfer controller. in the cpu interrupt-handling sequence, the t bit of the cpu status register is cleared to 0, and the interrupt mask level in bits i2 to i0 is set to the value in the ipr. unlike external interrupt requests, internal interrupt requests are not held in the interrupt controller, so the bits that generate internal interrupts must be cleared by software. 101
5.2.3 interrupt vector table table 5-2 lists the addresses of the exception vector table entries for each interrupt, and explains how their priority is determined. for the on-chip supporting modules, the priority level set in the interrupt priority register applies to the module as a whole: all interrupts from that module have the same priority level. a separate priority order is established among interrupts from the same module. if the same priority level is assigned to two or more modules and two interrupts are requested simultaneously from these modules, they are served in the priority order indicated in the rightmost column in table 5-2. a reset clears the interrupt priority registers so that all interrupts except nmi start with priority level 0, meaning that they are unconditionally masked. 102
table 5-2 interrupts, vectors, and priorities * if two or more interrupts are requested simultaneously, they are handled in order of priority level, as set in registers ipra to iprf. if they have the same priority level because they are requested from the same on-chip supporting module, they are handled in a fixed priority order within the module. if they are requested from different modules to which the same priority level is assigned, they are handled in the order indicated in the right-hand column. assignable priority priority vector table among levels priority entry address interrupts (initial ipr within minimum maximum on same interrupt level) bits module mode mode level * nmi 8(8) h'16 - h'17 h'2c - h'2f high irq 0 7 to 0 ipra 1 h'40 - h'41 h'80 - h'83 interval timer (0) bits 6 to 4 0 h'42 - h'43 h'84 - h'87 irq 1 7 to 0 ipra h'48 - h'49 h'90 - h'93 (0) bits 2 to 0 irq 2 7 to 0 iprb 1 h'50 - h'51 h'a0 - h'a3 irq 3 (0) bits 6 to 4 0 h'52 - h'53 h'a4 - h'a7 irq 4 7 to 0 iprb 1 h'58 - h'59 h'b0 - h'b3 irq 5 (0) bits 2 to 0 0 h'5a - h'5b h'b4 - h'b7 frt1 ici 7 to 0 iprc 3 h'60 - h'61 h'c0 - h'c3 ocia (0) bits 6 to 4 2 h'62 - h'63 h'c4 - h'c7 ocib 1 h'64 - h'65 h'c8 - h'cb fovi 0 h'66 - h'67 h'cc - h'cf frt2 ici 7 to 0 iprc 3 h'68 - h'69 h'd0 - h'd3 ocia (0) bits 2 to 0 2 h'6a - h'6b h'd4 - h'd7 ocib 1 h'6c - h'6d h'd8 - h'db fovi 0 h'6e - h'6f h'dc - h'df frt3 ici 7 to 0 iprd 3 h'70 - h'71 h'e0 - h'e3 ocia (0) bits 6 to 4 2 h'72 - h'73 h'e4 - h'e7 ocib 1 h'74 - h'75 h'e8 - h'eb fovi 0 h'76 - h'77 h'ec - h'ef 8-bit cmia 7 to 0 iprd 2 h'78 - h'79 h'f0 - h'f3 timer cmib (0) bits 2 to 0 1 h'7a - h'7b h'f4 - h'f7 ovi 0 h'7c - h'7d h'f8 - h'fb sci1 eri 7 to 0 ipre 2 h'80 - h'81 h'100 - h'103 rxi (0) bits 6 to 4 1 h'82 - h'83 h'104 - h'107 txi 0 h'84 - h'85 h'108 - h'10b sci2 eri 7 to 0 ipre 2 h'88 - h'89 h'110 - h'113 rxi (0) bits 2 to 0 1 h'8a - h'8b h'114 - h'117 txi 0 h'8c - h'8d h'118 - h'11b a/d adi 7 to 0 iprf h'90 - h'91 h'120 - h'123 converter (0) bits 6 to 4 low 103
5.3 register descriptions 5.3.1 interrupt priority registers a to f (ipra to iprf) irq 0 , irq 1 to irq 5 , and the on-chip supporting modules are each assigned three bits in one of the six interrupt priority registers (ipra to iprf). these bits specify a priority level from 7 (high) to 0 (low) for interrupts from the corresponding source. the drawing below shows the configuration of the interrupt priority registers. table 5-3 lists their assignments to interrupt sources. note: bits 7 and 3 are reserved. they cannot be modified and are always read as 0. table 5-3 assignment of interrupt priority registers as table 5-3 indicates, each interrupt priority register specifies priority levels for two interrupt sources. a user program can assign desired levels to these interrupt sources by writing ?00?in bits 6 to 4 or bits 2 to 0 to set priority level 0, for example, or ?11?to set priority level 7. a reset clears registers ipra to iprf to h'00, so all interrupts except nmi are initially masked. bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r r/w r/w r/w interrupt request source register bits 6 to 4 bits 2 to 0 ipra irq 0 irq 1 iprb irq 2 , irq 3 irq 4 , irq 5 iprc frt1 frt2 iprd frt3 8-bit timer ipre sci1 sci2 iprf a/d converter 104
when the interrupt controller receives one or more interrupt requests, it selects the request with the highest priority and compares its priority level with the interrupt mask level set in bits i2 to i0 in the cpu status register. if the priority level is higher than the mask level, the interrupt controller passes the interrupt request to the cpu (or starts the data transfer controller). if the priority level is lower than the mask level, the interrupt controller leaves the interrupt request pending until the interrupt mask is altered to a lower level or the interrupt priority is raised. similarly, if it receives two interrupt requests with the same priority level, the interrupt controller determines their priority as explained in table 5-2 and leaves the interrupt request with the lower priority pending. 5.3.2 timing of priority setting the interrupt controller requires two system clock (? periods to determine the priority level of an interrupt. accordingly, when an instruction modifies an instruction priority register, the new priority does not take effect until after the next instruction has been executed. 5.4 interrupt handling sequence 5.4.1 interrupt handling flow the interrupt-handling sequence follows the flowchart in figure 5-2. note that address error, trace exception, and nmi requests bypass the interrupt controllers priority decision logic and are routed directly to the cpu. 1. interrupt requests are generated by one or more on-chip supporting modules or external interrupt sources. 2. the interrupt controller checks the interrupt priorities set in ipra to iprf and selects the interrupt with the highest priority. interrupts with lower priorities remain pending. among interrupts with the same priority level, the interrupt controller determines priority as explained in table 5-2. 3. the interrupt controller compares the priority level of the selected interrupt request with the mask level in the cpu status register (bits i2 to i0). if the priority level is equal to or less than the mask level, the interrupt request remains pending. if the priority level is higher than the mask level, the interrupt controller accepts the interrupt request and proceeds to the next step. 4. the interrupt controller checks the corresponding bit (if any) in the data transfer enable registers (dtea to dtef). if this bit is set to 1, the data transfer controller is started. otherwise, the cpu interrupt exception-handling sequence is started. when the data transfer controller is started, the interrupt request is cleared (except for interrupt requests from the serial communication interface, which are cleared by writing to the tdr or reading the rdr). 105
if the data transfer enable bit is cleared to 0 (or is nonexistent), the sequence proceeds as follows. for the case in which the data transfer controller is started, see section 6, ?ata transfer controller. 5. after the cpu has finished executing the current instruction, the program counter and status register (in minimum mode) or program counter, code page register, and status register (in maximum mode) are saved to the stack, leaving the stack in the condition shown in figure 5-3 (a) or (b). the program counter value saved on the stack is the address of the next instruction to be executed. 6. the t (trace) bit of the status register is cleared to 0, and the priority level of the interrupt is copied to bits i2 to i0, thus masking further interrupts unless they have a higher priority level. when an nmi is accepted, the interrupt mask level in bits i2 to i0 is set to 7. 7. the interrupt controller generates the vector address of the interrupt, and the entry at this address in the exception vector table is read to obtain the starting address of the user-coded interrupt handling routine. in step 7, the same difference between the minimum and maximum modes exists as in the reset handling sequence. in the minimum mode, one word is copied from the vector table to the program counter, then the interrupt-handling routine starts executing from the address indicated in the program counter. in the maximum mode, two words are read. the lower byte of the first word is copied to the code page register. the second word is copied to the program counter. the interrupt-handling routine starts executing from the address indicated in the code page register and program counter. 106
program execution state interrupt requested? y n n n n n n n n n n y y y y y y y y y y n n y y n n n n y y y n address error? trace? nmi? level-7 interrupt? level-6 interrupt? level-1 interrupt? mask level in sr 6? mask level in sr 5? mask level in sr = 0? data transfer enabled? interrupt remains pending start dtc read dtc vector read transfer mode read source address read data source address increment mode? increment source address (+1 or +2) write source address read destination address write data exception-handling sequence save pc maximum mode? save sr save pc clear t bit trace address error? update mask level vectoring destination address increment mode? write destination address increment source address (+1 or +2) read dtcr dtcr-1 dtcr ? write dtcr dtcr = 0? to user-coded exception-handling routine figure 5-2 interrupt handling flowchart 107
5.4.2 stack status after interrupt handling sequence figure 5-3 (a) and (b) show the stack before and after the interrupt exception-handling sequence. sp address fig. 5-3(a) sp 2m ?4 2m ?3 2m ?2 2m ?1 2m address 2m ?4 2m ?3 2m ?2 2m ?1 2m upper 8 bits of sr lower 8 bits of sr upper 8 bits of pc lower 8 bits of pc (after) (before) stack area save to stack notes: 1. pc: the address of the next instruction to be executed is saved. 2. register saving and restoring must start at an even address (e.g 2m). figure 5-3 (a) stack before and after interrupt exception-handling (minimum mode) 108
5.4.3 timing of interrupt exception-handling sequence figure 5-4 shows the timing of the exception-handling sequence for an interrupt in minimum mode when the program area and stack area are both in on-chip memory and the user-coded interrupt handling routine starts at an even address. figure 5-5 shows the timing of the exception-handling sequence for an interrupt in maximum mode when the program area and stack area are both in external memory. 5.5 interrupts during operation of the data transfer controller if an interrupt is requested during a dtc data transfer cycle, the interrupt is not accepted until the data transfer cycle has been completed and the next instruction has been executed. this is true even if the interrupt is an nmi. an example is shown below. sp address fig. 5-3(b) sp 2m ?4 2m ?3 2m ?2 2m ?1 2m address 2m ?4 2m ?3 2m ?2 2m ?1 2m upper 8 bits of sr cp upper 8 bits of pc lower 8 bits of pc (after) (before) stack area save to stack notes: 1. pc: the address of the next instruction to be executed is saved. 2. register saving and restoring must start at an even address (e.g 2m). 2m ?5 2m ?6 2m ?5 2m ?6 lower 8 bits of sr don? care add.w r2, r0 mov.w r0, @h'fe00 add.w @h' fe02,r0 program flow dtc interrupt request data transfer cycle nmi interrupt after data transfer cycle, cpu executes next instruction before starting exception handling to nmi exception handling sequence (example) figure 5-3 (b) stack before and after interrupt exception-handling (maximum mode) 109
(3) vector address sp - 4 sp - 2 (4) vector sr pc (2) (2) (2) (1) (1) (1) nmi, irq 0 irq to irq 1 interrupt address bus internal data bus (16 bits) internal read signal internal write signal priority level decision and wait for end of current instruction stack access internal process- ing cycle prefetch first instruction of interrupt- handling routine start instruction execution interrupt accepted (1) instruction prefetch address (2) instruction code (3) starting address of interrupt-handling routine (4) first instruction of interrupt-handling routine note: this timing chart applies to the minimum mode when the program and stack areas are both in on-chip memory and the interrupt-handling routine starts at an even address. 5 figure 5-4 interrupt sequence (minimum mode, on-chip memory) 110
nmi, irq 0 irq to irq 1 internal address bus internal data bus (16 bits) internal read signal internal write signal priority level decision and wait for end of current instruction (1) instruction prefetch address (2) instruction code (3) starting address of interrupt-handling routine (4) first instruction of interrupt-handling routine internal processing cycle stack access interrupt vector prefetch first instruction of interrupt-handling routine start instruction execution note: this timing chart applies to the maximum mode when the program and stack areas are both in external memory. instruction execution starts after interrupt vector fetch and 4-byte (4 bys cycles) instruction prefetch has been done. (1) (1) sp ?2 sp ?1 sp ?4 sp ?3 sp ?6 sp ?5 vector vector address address + 1 address + 2 address + 3 vector vector (3) (2) (2) pc h pc l cp sr l sr h don? care vector vector vector (4) don? care 5 figure 5-5 interrupt sequence (maximum mode, external memory) 111
5.6 interrupt response time table 5-4 indicates the number of states that may elapse between the generation of an interrupt request and the execution of the first instruction of the interrupt-handling routine, assuming that the interrupt is not masked and not preempted by a higher-priority interrupt. since word access is performed to on-chip memory areas, fastest interrupt service can be obtained by placing the program in on-chip rom and the stack in on-chip ram. table 5-4 number of states before interrupt service note: m: number of wait states inserted in external memory access. values in parentheses are for the ldm instruction. number of states no. reason for wait minimum mode maximum mode 1 interrupt priority decision and comparison with 2 states mask level in cpu status register 2 maximum number of instruction is in on-chip x states to completion memory (x = 38 for ldm instruction specifying of current instruction all registers) instruction is in external y memory (y = 74 + 16m for ldm instruction specifying all registers) 3 saving of pc and sr stack is in on-chip ram 16 21 or pc, cp, and sr stack is in external memory 28 + 6m 41 + 10m and instruction prefetch stack is in instruction is in on-chip 18 + x 23 + x on-chip ram memory (56) (61) instruction is in external 18 + y 23 + y total memory (92 + 16m) (97 + 16m) stack is in instruction is in on-chip 30 + 6m + x 43 + 10m + x external ram memory (68 + 6m) (81 + 10m) instruction is in external 30 + 6m + y 43 + 10m + y memory (104 + 22m) (117 + 26m) 112
section 6 data transfer controller 6.1 overview the h8/534 and h8/536 include a data transfer controller (dtc) that can be started by designated interrupts to transfer data from a source address to a destination address located in page 0. these addresses include in particular the registers of the on-chip supporting modules and i/o ports. typical uses of the dtc are to change the setting of a control register of an on-chip supporting module in response to an interrupt from that module, or to transfer data from memory to an i/o port or the serial communication interface. once set up, the transfer is interrupt-driven, so it proceeds independently of program execution, although program execution temporarily stops while each byte or word is being transferred. 6.1.1 features the main features of the dtc are listed below. the source address and destination address can be set anywhere in the 64-kbyte address space of page 0. the dtc can be programmed to transfer one byte or one word of data per interrupt. the dtc can be programmed to increment the source address and/or destination address after each byte or word is transferred. after transferring a designated number of bytes or words, the dtc generates a cpu interrupt with the vector of the interrupt source that started the dtc. this designated data transfer count can be set from 1 to 65,536 bytes or words. 6.1.2 block diagram figure 6-1 shows a block diagram of the dtc. the four dtc control registers (dtmr, dtsr, dtdr, and dtcr) are invisible to the cpu, but corresponding information is kept in a register information table in memory. a separate table is maintained for each dtc interrupt type. when an interrupt requests dtc service, the dtc loads its control registers from the table in memory, transfers the byte or word of data, and writes any altered register information back to memory. 113
6.1.3 register configuration the four dtc control registers are listed in table 6-1. these registers are not located in the address space and cannot be written or read by the cpu. to set information in these registers, a program must write the information in a table in memory from which it will be loaded by the dtc. table 6-1 internal control registers of the dtc name abbreviation read/write data transfer mode register dtmr disabled data transfer source address register dtsr disabled data transfer destination address register dtdr disabled data transfer count register dtcr disabled irq 0 irq 1 internal data bus dtc request dtc interrupt controller dtec dted dtee dtef dtmr dtsr dtdr dtcr dtmr: dtsr: dtdr: dtcr: dtea to dtef: dt mode register dt source address register dt destination address register dt count register dt enable register a to d ram register information table 0 register information table 1 dtea dteb figure 6-1 block diagram of data transfer controller 114
starting of the dtc is controlled by the six data transfer enable registers, which are located in high addresses in page 0. table 6-2 lists these registers. table 6-2 data transfer enable registers name abbreviation read/write address initial value data transfer enable register a dtea r/w h'ff08 h'00 data transfer enable register b dteb r/w h'ff09 h'00 data transfer enable register c dtec r/w h'ff0a h'00 data transfer enable register d dted r/w h'ff0b h'00 data transfer enable register e dtee r/w h'ff0c h'00 data transfer enable register f dtef r/w h'ff0d h'00 6.2 register descriptions 6.2.1 data transfer mode register (dtmr) the data transfer mode register is a 16-bit register, the first three bits of which designate the data size and specify whether to increment the source and destination addresses. bit 15?z (size): this bit designates the size of the data transferred. bit 15 sz description 0 byte transfer 1 word transfer* (two bytes at a time) * for word transfer, the source and destination addresses must be even addresses. bit 14?i (source increment): this bit specifies whether to increment the source address. bit 14 si description 0 source address is not incremented. 1 1) if sz = 0: source address is incremented by +1 after each data transfer. 2) if sz = 1: source address is incremented by +2 after each data transfer. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sz si di read/write 115
bit 13?i (destination increment): this bit specifies whether to increment the destination address. bit 13 di description 0 destination address is not incremented. 1 1) if sz = 0: destination address is incremented by +1 after each data transfer. 2) if sz = 1: destination address is incremented by +2 after each data transfer. bits 12 to 0?eserved bits: these bits are reserved. 6.2.2 data transfer source address register (dtsr) the data transfer source register is a 16-bit register that designates the data transfer source address. for word transfer this must be an even address. in the maximum mode, this address is implicitly located in page 0. 6.2.3 data transfer destination register (dtdr) the data transfer destination register is a 16-bit register that designates the data transfer destination address. for word transfer this must be an even address. in the maximum mode, this address is implicitly located in page 0. 6.2.4 data transfer count register (dtcr) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read/write bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read/write bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 read/write 116
the data transfer count register is a 16-bit register that counts the number of bytes or words of data remaining to be transferred. the initial count can be set from 1 to 65,536. a register value of 0 designates an initial count of 65,536. the data transfer count register is decremented automatically after each byte or word is transferred. when its value reaches 0, indicating that the designated number of bytes or words have been transferred, a cpu interrupt is generated with the vector of the interrupt that requested the data transfer . 6.2.5 data transfer enable registers a to f (dtea to dtef) these six registers designate whether an interrupt starts the dtc. the bits in these registers are assigned to interrupts as indicated in table 6-3. no bits are assigned to the nmi, fovi, ovi, and eri interrupts, which cannot request data transfers. table 6-3 assignment of data transfer enable registers note: bits marked ?should always be cleared to 0. if the bit for a certain interrupt is set to 1, that interrupt is regarded as a request for dtc service. if the bit is cleared to 0, the interrupt is regarded as a cpu interrupt request. bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w interrupt interrupt source or source or register module bits 7 to 4 module bits 3 to 0 7 6 5 4 3 2 1 0 dtea irq 0 irq 0 irq 1 irq 1 dteb irq 2 , irq 3 irq 3 irq 2 irq 4 , irq 5 irq 5 irq 4 dtec 16-bit frt1 ocib1 ocia1 ici1 16-bit frt2 ocib2 ocia2 ici2 dted 16-bit frt3 ocib3 ocia3 ici3 8-bit timer cmib cmia dtee sci1 txi1 rxi1 sci2 txi2 rxi2 dtef a/d converter adi 117
only the interrupts indicated in table 6-3 can request dtc service. dte bits not assigned to any interrupt (indicated by ?in table 6-3) should be left cleared to 0. ? note on timing of dte modifications: the interrupt controller requires two system clock (? periods to determine the priority level of an interrupt. accordingly, when an instruction modifies a data transfer enable register, the new setting does not take effect until the third state after taht instruction has been executed. 6.3 data transfer operation 6.3.1 data transfer cycle when started by an interrupt, the dtc executes the following data transfer cycle: 1. from the dtc vector table, the dtc reads the address at which the register information table for that interrupt is located in memory. 2. the dtc loads the data transfer mode register and source address register from this table and reads the data (one byte or word) from the source address. 3. if so specified in the mode register, the dtc increments the source address register and writes the new source address back to the table in memory. 4. the dtc loads the data transfer destination address register and writes the byte or word of data to the destination address. 5. if so specified in the mode register, the dtc increments the destination address register and writes the new destination address back to the table in memory. 6. the dtc loads the data transfer count register from the table in memory, decrements the data count, and writes the new count back to memory. 7. if the data transfer count is now 0, the dtc generates a cpu interrupt. the interrupt vector is the vector of the interrupt type that started the dtc. at an appropriate point during this procedure the dtc also clears the interrupt request by clearing the corresponding flag bit in the status register of the on-chip supporting module to 0. but the dtc does not clear the data transfer enable bit in the data transfer enable register. this action, if necessary, must be taken by the user-coded interrupt-handling routine invoked at the end of the transfer. the data transfer cycle is shown in a flowchart in figure 6-2. for the steps from the occurrence of the interrupt up to the start of the data transfer cycle, see section 5.4.1, ?nterrupt handling flow. 118
int interrupt dtc interrupt? n y dtc read dtc vector read transfer mode read source address read data source address increment mode? n y read destination address write data destination address increment mode? n y increment source address (+1 or +2) write source address write destination address increment destination address (+1 or +2) read dtcr dtcr e 1 dtcr ? write dtcr dtcr = 0? y n dtc end cpu save pc and sr read vector read address from vector table start executing interrupt-handling routine at that address. figure 6-2 flowchart of data transfer cycle 119
6.3.2 dtc vector table the dtc vector table is located immediately following the exception vector table at the beginning of page 0 in memory. for each interrupt that can request dtc service, the dtc vector table provides a pointer to an address in memory where the table of dtc control register information for that interrupt is stored. the register information tables can be placed in any available locations in page 0. in minimum mode, each entry in the dtc vector table consists of two bytes, pointing to an address in page 0. in maximum mode, for compatibility reasons, each dtc vector table entry consists of four bytes but the first two bytes are ignored; the last two bytes point to an address which is implicitly assumed to be in page 0, regardless of the current page specifications. figure 6-4 shows one dtc vector table entry in minimum and maximum mode. vector table exception vector table ta 0 dtc vector table register information table 0 ram register information table 1 dtmr0 dtsr0 dtdr0 dtcr0 dtmr1 dtsr1 dtdr1 dtcr1 ta 1 ta 1 ta 0 note: ta , ta ,... : addresses of dtc register information tables in memory. 0 1 note: ta 0 , ta 1 , ...: addresses of dtc register information tables in memory. normally the register information tables are placed on ram. if software does not need to modify the register information (addresses are fixed and transfer count is 1), it can be placed on rom. figure 6-3 dtc vector table 120
table 6-4 lists the addresses of the entries in the dtc vector table for each interrupt. table 6-4 addresses of dtc vectors dtc vector table fig. 6-4 address m m + 1 address (h) address (l) ram dtc vector table register information (1) minimum mode address 2m 2 m + 1 don? care don? care (2) maximum mode 2 m + 2 address (h) 2 m + 3 address (l) * * * address 2m and 2m + 1 are not accessed at vector read. address of dtc vector interrupt minimum mode maximum mode irq 0 h'00c0 - h'00c1 h'0180 - h'0183 interval timer h'00c2 - h'00c3 h'0184 - h'0187 irq 1 h'00c8 - h'00c9 h'0190 - h'0193 irq 2 h'00d0 - h'00d1 h'01a0 - h'01a3 irq 3 h'00d2 - h'00d3 h'01a4 - h'01a7 irq 4 h'00d8 - h'00d9 h'01b0 - h'01b3 irq 5 h'00da - h'00db h'01b4 - h'01b7 frt1 ici h'00e0 - h'00e1 h'01c0 - h'01c3 ocia h'00e2 - h'00e3 h'01c4 - h'01c7 ocib h'00e4 - h'00e5 h'01c8 - h'01cb frt2 ici h'00e8 - h'00e9 h'01d0 - h'01d3 ocia h'00ea - h'00eb h'01d4 - h'01d7 ocib h'00ec - h'00ed h'01d8 - h'01db frt3 ici h'00f0 - h'00f1 h'01e0 - h'01e3 ocia h'00f2 - h'00f3 h'01e4 - h'01e7 ocib h'00f4 - h'00f5 h'01e8 - h'01eb figure 6-4 dtc vector table entry 121
table 6-4 addresses of dtc vectors (cont) 6.3.3 location of register information in memory for each interrupt, the dtc control register information is stored in four consecutive words in memory in the order shown in figure 6-5. 6.3.4 length of data transfer cycle table 6-5 lists the number of states required per data transfer, assuming that the dtc control register information is stored in on-chip ram. this is the number of states required for loading and saving the dtc control registers and transferring one byte or word of data. two cases are considered: a transfer between on-chip ram and a register belonging to an i/o port or on-chip supporting module (i.e., a register in the register field from addresses h'fe80 to h'ffff); and a transfer between such a register and external ram. address of dtc vector interrupt minimum mode maximum mode 8-bit cmia h'00f8 - h'00f9 h'01f0 - h'01f3 timer cmib h'00fa - h'00fb h'01f4 - h'01f7 sci1 rxi h'00a2 - h'00a3 h'0144 - h'0147 txi h'00a4 - h'00a5 h'0148 - h'014b sci2 rxi h'00aa - h'00ab h'0154 - h'0157 txi h'00ac - h'00ad h'0158 - h'015b a/d converter adi h'00b0 - h'00b1 h'0160 - h'0163 dtc vector table fig. 6-5 ta ta + 2 ram dtmr dtsr dtdr dtcr 8 bits 8 bits ta + 4 ta + 6 mode register source address register destination address register count register figure 6-5 order of register information 122
table 6-5 number of states per data transfer note: numbers in the table are the number of states. the values in table 6-5 are calculated from the formula: n = 26 + 2 si + 2 di + m s + m d where m s and m d have the following meanings: m s : number of states for reading source data m d : number of states for writing destination data the values of m s and m d depend on the data location as follows: byte or word data in on-chip ram: 2 states byte data in external ram or register field: 3 states a word data in external ram or register field: 6 states if the dtc control register information is stored in external ram, 20 + 4 si + 4 di must be added to the values in table 6-5. the values given above do not include the time between the occurrence of the interrupt request and the starting of the dtc. this time includes two states for the interrupt controller to check priority and a variable wait until the end of the current cpu instruction. at maximum, this time equals the sum of the values indicated for items no. 1 and 2 in table 6-6. if the data transfer count is 0 at the end of a data transfer cycle, the number of states from the end of the data transfer cycle until the first instruction of the user-coded interrupt-handling routine is executed is the value given for item no. 3 in table 6-6. increment mode on-chip ram ? module or i/o external ram ? module or i/o source destina- register register (si) tion (di) byte transfer word transfer byte transfer word transfer 0 0 31 34 32 38 0 1 33 36 34 40 1 0 33 36 34 40 1 1 35 38 36 42 123
table 6-6 number of states before interrupt service m: number of wait states inserted in external memory access 6.4 procedure for using the dtc a program that uses the dtc to transfer data must do the following: 1. set the appropriate dtmr, dtsr, dtdr, and dtcr register information in the memory location indicated in the dtc vector table. 2. set the data transfer enable bit of the pertinent interrupt to 1, and set the priority of the interrupt source (in the interrupt priority register) and the interrupt mask level (in the cpu status register) so that the interrupt can be accepted. 3. set the interrupt enable bit in the control register for the interrupt source (or set the irq enable bit). following these preparations, the dtc will be started each time the interrupt occurs. when the number of bytes or words designated by the dtcr value have been transferred, after transferring the last byte or word, the dtc generates a cpu interrupt. the user-coded interrupt-handling routine must take action to prepare for or disable further dtc data transfer: by readjusting the data transfer count, for example, or clearing the interrupt enable bit. if no action is taken, the next interrupt of the same type will start the dtc with an initial data transfer count of 65,536. number of states no. reason for wait minimum mode maximum mode 1 interrupt priority decision and comparison with 2 states mask level in cpu status register 2 maximum number of instruction is in on-chip 38 states to completion memory (ldm instruction specifying all registers) of current instruction instruction is in external 74 + 16m memory (ldm instruction specifying all registers) 3 saving of pc and sr stack is in on-chip ram 16 21 or pc, cp, and sr and instruction prefetch stack is in external memory 28 + 6m 41 + 10m 124
6.5 example purpose: to receive 128 bytes of serial data the serial communication interface 1. conditions: operating mode: minimum mode received data are to be stored in consecutive addresses starting at h'fc00. dtc control register information for the rxi interrupt is stored at addresses h'fb80 to h'fb87. accordingly, the dtc vector table contains h'fb at address h'00a2 and h'80 at address h'00a3. the desired interrupt mask level in the cpu status register is 4, and the desired sci1 interrupt priority level is 5. procedure 1. the user program sets dtc control register information in addresses h'fb80 to h'fb87 as shown in table 6-7. table 6-7 dtc control register information set in ram 2. the program sets the ri (sci1 receive interrupt) bit in the data transfer enable register (bit 5 of register dtee) to 1. 3. the program sets the interrupt mask in the cpu status register to 4, and the sci1 interrupt priority in bits 6 to 4 of interrupt priority register ipre to 5. 4. the program sets sci1 to the appropriate receive mode, and sets the receive interrupt enable (rie) bit in the serial control register (scr) to 1 to enable receive interrupts. 5. thereafter, each time sci1 receives one byte of data, it requests an rxi interrupt, which the interrupt controller directs toward the dtc. the dtc transfers the byte from the scis receive data register (rdr) into ram, and clears the interrupt request before ending. address register description value set byte transfer h'fb80 dtmr source address fixed h'2000 increment destination address h'fb82 dtsr address of sci1 receive data register h'fedd h'fb84 dtdr address h'fc00 h'fc00 h'fb86 dtcr number of bytes to be received: 128 h'0080 125
6. when 128 bytes have been transferred (dtcr = 0), the dtc generates a cpu interrupt. the interrupt type is rxi from sci1. 7. the user-coded rxi interrupt-handling routine processes the received data and disables further data transfer (by clearing the rie bit, for example). figure 6-6 shows the dtc vector table and data in ram for this example. address h'00a2 h'00a3 h'fb h'80 dtc vector table ram address h'fb80 h'fb81 h'20 h'00 h'fe h'dd h'fc h'00 h'00 h'80 h'fb87 h'fc00 h'fc7f sci receive data 1 receive data 2 receive data 128 rdr transferred by dtc mode source address destination address counter figure 6-6 use of dtc to receive data via serial communication interface 1 126
section 7 wait-state controller 7.1 overview to simplify interfacing to low-speed external devices, the h8/534 and h8/536 have an on-chip wait-state controller (wsc) that can insert wait states (t w ) to prolong bus cycles. the wait-state function can be used in cpu and dtc access cycles to external addresses. it is not used in access to on-chip supporting modules. the t w states are inserted between the t 2 state and t 3 state in the bus cycle. the number of wait states can be selected by a value set in the wait- state control register (wcr), or by holding the wait pin low for the required interval. 7.1.1 features the main features of the wait-state controller are: selection of three operating modes programmable wait mode, pin wait mode, or pin auto-wait mode 0, 1, 2, or 3 wait states can be inserted. and in the pin wait mode, 4 or more states can be inserted by holding the wait pin low. 127
7.1.2 block diagram figure 7-1 shows a block diagram of the wait-state controller. 7.1.3 register configuration the wait-state controller has one control register: the wait-state control register described in table 7-1. table 7-1 register configuration name abbreviation read/write initial value address wait-state control register wcr r/w h'f3 h'ff10 fig. 7-1 internal data bus wait input wcr: wms1, 0: wc1, 0: control logic wcr wms1 wms0 wc1 wc0 wait counter wait request wait-state control register wait mode select 1, 0 wait count 1, 0 figure 7-1 block diagram of wait-state controller 128
7.2 wait-state control register the wait-state control register (wcr) is an 8-bit register that specifies the wait mode and the number of wait states to be inserted. a reset initializes the wcr to specify the programmable wait mode with three wait states. the wcr is not initialized in the software standby mode. bits 7 to 4?eserved: these bits cannot be modified and are always read as 1. bits 3 and 2?ait mode select 1 and 0 (wms1 and wms0): these bits select the wait mode as shown below. bits 1 and 0?ait count (wc1 and wc0): these bits specify the number of wait states to be inserted. wait states are inserted only in bus cycles in which the cpu or dtc accesses an external address. bit 7 6 5 4 3 2 1 0 wms1 wms0 wc1 wc0 initial value 1 1 1 1 0 0 1 1 read/write r/w r/w r/w r/w bit 3 bit 2 wms1 wms0 description 0 0 programmable wait mode (initial value) 0 1 no wait states are inserted, regardless of the wait count. 1 0 pin wait mode 1 1 pin auto-wait mode bit 1 bit 0 wc1 wc0 description 0 0 no wait states are inserted, except in pin wait mode. 0 1 1 wait state is inserted. 1 0 2 wait states are inserted. 1 1 3 wait states are inserted. (initial value) 129
7.3 operation in each wait mode table 7-2 summarizes the operation of the three wait modes. table 7-2 wait modes wait insertion number of wait mode pin function conditions states inserted programmable disabled inserted on access to 1 to 3 wait states are inserted, as wait mode an off-chip address specified by bits wc0 and wc1. wms1 = 0 wms0 = 0 pin wait mode enabled inserted on access to 0 to 3 wait states are inserted, as wms1 = 1 an off-chip address specified by bits wc0 and wc1, wms0 = 0 plus additional wait states while the wait pin is held low. pin auto-wait enabled inserted on access to 1 to 3 wait states are inserted, as mode an off-chip address if specified by bits wc0 and wc1. wms1 = 1 the wait pin is low wms0 = 1 7.3.1 programmable wait mode the programmable wait mode is selected when wms1 = 0 and wms0 = 0. whenever the cpu or dtc accesses an off-chip address, the number of wait states set in bits wc1 and wc0 are inserted. the wait pin is not used for wait control; it is available as an i/o pin. 130
figure 7-2 shows the timing of the operation in this mode when the wait count is 1 (wc1 = 0, wc0 = 1). 7.3.2 pin wait mode the pin wait mode is selected when wms1 = 1 and wms0 = 0. in this mode the wait function of the p1 4 /wait pin is used automatically. the number of wait states indicated by bits wc1 and wc0 are inserted into any bus cycle in which the cpu or dtc accesses an off-chip address. in addition, wait states continue to be inserted as long as the wait pin is held low. in particular, if the wait count is 0 but the wait pin is low at the rising edge of the ?clock in the t 2 state, wait states are inserted until the wait pin goes high. this mode is useful for inserting four or more wait states, or when different external devices require different numbers of wait states. t rd, as, ds (read) d ? 7 0 a ? 19 0 d ? 7 0 wr, ds (write) read data off-chip address read data write data 2 state or t 3 t 1 t 2 t w t 3 fig. 7-2 figure 7-2 programmable wait mode 131
figure 7-3 shows the timing of the operation in this mode when the wait count is 1 (wc1 = 0, wc0 = 1) and the wait pin is held low to insert one additional wait state. rd, as, ds (read) d ? 7 0 d ? 7 0 wr, ds (write) a ? 19 0 wait pin off-chip address write data read data t 2 t 1 t w wait count t w t 3 wait pin * * fig. 7-3 * the arrowheads indicate the times at which the wait pin is sampled. figure 7-3 pin wait mode 132
7.3.3 pin auto-wait mode the pin auto-wait mode is selected when wms1 = 1 and wms0 = 1. in this mode the wait function of the p1 4 /wait pin is used automatically. in this mode, the number of wait states indicated by bits wc1 and wc0 are inserted, but only if there is a low input at the wait pin. figure 7-4 shows the timing of this operation when the wait count is 1. in the pin auto-wait mode, the wait pin is sampled only once, on the falling edge of the ?clock in the t 2 state. if the wait pin is low at this time, the wait-state controller inserts the number of wait states indicated by bits wc1 and wc0. the wait pin is not sampled during the tw and t 3 states, so no additional wait states are inserted even if the wait pin continues to be held low. this mode offers a simple way to interface a low-speed device: the wait states can be inserted by routing a decoded address signal to the wait pin. rd, as, ds (read) d ? 7 0 d ? 7 0 wr, ds (write) a ? 19 0 wait fig. 7-4 external address external address read data read data write data write data * * t 1 t 2 t 3 t 1 t 2 t 3 t w * the arrowheads indicate the times at which the wait pin is sampled. figure 7-4 pin auto-wait mode 133
section 8 clock pulse generator 8.1 overview the h8/534 and h8/536 have a built-in clock pulse generator (cpg) consisting of an oscillator circuit, a system (? clock divider, an e clock divider, and a group of prescalers. the prescalers generate clock signals for the on-chip supporting modules. 8.1.1 block diagram 8.2 oscillator circuit if an external crystal is connected across the extal and xtal pins, the on-chip oscillator circuit generates a clock signal for the system clock divider. alternatively, an external clock signal can be applied to the extal pin. connecting an external crystal (1) circuit configuration: an external crystal can be connected as in the example in figure 8-2. an at-cut parallel resonating crystal should be used. xtal extal e ?2 to ?4096 oscillator circuit divider ?2 divider ?8 cpg prescalers figure 8-1 block diagram of clock pulse generator 135
(2) crystal oscillator: the external crystal should have the characteristics listed in table 8-1. table 8-1 (1) external crystal parameters (hd6475368r, hd6475348r, hd6435368r, hd6435348r) frequency (mhz) 2 4 8 12 16 20 rs max ( ) 500 120 60 40 30 20 c 0 (pf) 7pf max table 8-1 (2) external crystal parameters (hd6475368s, hd6475348s, hd6435368s, hd6435348s) frequency (mhz) 4 8 12 16 20 24 rs max ( ) 120 80 60 50 40 40 c 0 (pf) 7pf max note: use a fundamental-mode crystal (not an overtone crystal). (3) note on board design: when an external crystal is connected, other signal lines should be kept away from the crystal circuit to prevent induction from interfering with correct oscillation. see figure 8-4. when the board is designed, the crystal and its load capacitors should be placed as close as possible to the xtal and extal pins. extal c xtal l1 c l2 c =c =10 to 22pf l1 l2 fig. 8-3 c l xtal extal l r s c 0 at-cut parallel resonating crystal figure 8-2 connection of crystal oscillator (example) figure 8-3 crystal oscillator equivalent circuit 136
input of external clock signal (1) circuit configuration (hd6475368r, hd6475348r, hd6435368r, hd6435348r): when using an external clock, input complementary clock signals to the extal and xtal pins as shown in figure 8-5. make sure the external clock does not go high during standby mode. figure 8-5 external clock input (example) (2) external clock input frequency double the system clock (? frequency duty cycle 45% to 55% note: mask-rom versions can operate on external clock input to the extal pin alone, with the xtal pin left open. ztat ? versions can also operate with the xtal pin left open if the external clock frequency is 16 mhz or less. c l2 c l1 not allowed signal a signal b h8/534 h8/536 xtal extal figure 8-4 notes on board design around external crystal fig. 8-5 external clock input 74hc04 extal xtal 137
(3) circuit configuration (hd6475368s, hd6475348s, hd6435368s, hd6435348s): figure 8-6 shows examples of external clock input. when using figure 8-6 (b), make sure the external clock does not go high during standby mode. when the xtal pin is open, make sure the parasitic capacifance is less than 10 pf. (4) external clock input frequency double the system clock (? frequency duty cycle 40% to 60% external clock input 74hc04 extal xtal extal xtal open external clock input (a) xtal pin left open (b) complementary clock input at xtal pin figure 8-6 external clock input (examples) 138
8.3 system clock divider the system clock divider divides the crystal oscillator or external clock frequency (fosc) by 2 to create the ?clock. an e clock signal is created by dividing the ?clock by 8. the e clock is used for interfacing to e clock based devices. figure 8-7 shows the phase relationship of the e clock to the ?clock. figure 8-7 phase relationship of ?clock and e clock e 139
section 9 i/o ports 9.1 overview the h8/534 and h8/536 have nine ports. ports 1, 3, 4, 5, 7, and 9 are eight-bit input/output ports. port 2 is a five-bit input/output port. port 6 is a four-bit input/output port. port 8 is an eight-bit input-only port. table 9-1 summarizes the functions of each port. input and output are memory-mapped. the cpu views each port as a data register (dr) located in the register field at the high end of page 0 of the address space. each port (except port 8) also has a data direction register (ddr) which determines which pins are used for input and which for output. additional system control registers (syscr1 and syscr2) control the functions of pins in ports 1, 6, and 9. to read data from an i/o port, the cpu selects input in the data direction register and reads the data register. this causes the input logic level at the pin to be placed directly on the internal data bus. there is no intervening input latch. to send data to an output port, the cpu selects output in the data direction register and writes the desired data in the data register, causing the data to be held in a latch. the latch output drives the pin through a buffer amplifier. if the cpu reads the data register of an output port, it obtains the data held in the latch rather than the actual level of the pin. as table 9-1 indicates, all of the i/o port pins have dual functions. for example, pin 7 of port 1 can be used either as a general-purpose i/o pin (p1 7 ), or for output of the tmo signal from the on-chip 8-bit timer. the function is determined by the mcu operating mode, or by a value set in a control register. outputs from ports 1 to 6 can drive one ttl load and a 90 pf capacitive load. outputs from ports 7 and 9 can drive one ttl load and a 30 pf capacitive load. outputs from ports 1 to 7 and 9 can also drive a darlington transistor pair. outputs from port 4 can drive a light-emitting diode (with 10ma current sink). ports 5 and 6 have built-in mos pull- ups for each input. port 7 has schmitt inputs. schematic diagrams of the i/o port circuits are shown in appendix c. 141
table 9-1 input/output port summary expanded modes single-chip mode port description pins mode 1 mode 2 mode 3 mode 4 (mode 7) port 1 8-bit input/output p1 7 / tmo these input/output pins double as irq 1 , p1 6 / irq 1 / irq 0 , and adtrg inputs, and as an adtrg output pin (tmo) for the 8-bit timer. p1 5 / irq 0 p1 4 / wait these pins function as wait, breq, input/output p1 3 / breq and back when necessary control- port p1 2 / back register bits are set to 1. p1 1 / e these pins function as input pins or as p1 0 / clock (e, ? output pins, depending on the data direction register setting. port 2 5-bit input/output p2 4 / wr bus control signal outputs input/output port p2 3 / rd (wr, rd, ds, r/w, as) port p2 2 / ds p2 1 / r/w p2 0 / as port 3 8-bit input/output p3 7 - p3 0 / data bus (d 7 ?d 0 ) input/output port d 7 ?d 0 port port 4 8-bit input/output p4 7 ?p4 0 / low address bus (a 7 ?a 0 ) input/output port a 7 ?a 0 port can drive a led port 5 8-bit input/output p5 7 ?p5 0 / high high high high input/output port a 15 ?a 8 address address address address port built-in input bus bus if bus bus if pull-up (mos) (a 15 ddr is (a 15 ddr is a 8 ) set to 1 a 8 ) set to 1 port 6 4-bit input/output p6 3 / pw 3 / output for pwm page page input/output port irq 5 / a 19 timers 1, 2, and address address port built-in input p6 2 / pw 2 / 3, input for irq 2 bus bus if ddr pull-up (mos) irq 4 / a 18 to irq 5 , and (a 19 is set to 1, p6 1 / pw 1 / input/output port. a 16 ) input port irq 3 / a 17 and irq 2 p6 0 / irq 2 / to irq 5 a 16 input pins if ddr is set to 0 142
table 9-1 input/output port summary (cont) expanded modes single-chip mode port description pins mode 1 mode 2 mode 3 mode 4 (mode 7) port 7 8-bit input/output p7 7 / ftoa 1 input/output for free-running timers 1, port p7 6 / ftob 3 / 2 and 3 (fti 1 to fti 3 , ftci 1 to ftci 3 , (schmitt inputs) ftci 3 ftob 1 to ftob 3 , ftoa 1 ),input for p7 5 / ftob 2 / 8-bit timer input (tmci, tmri), and 8-bit ftci 2 input/output port p7 4 / ftob 1 / (p7 7 to p7 0 ) ftci 1 / p7 3 / fti 3 tmri p7 2 / fti 2 p7 1 / fti 1 p7 0 / tmci port 8 8-bit input port p8 0 ?p8 7 analog input pins for a/d converter, and an 7 ?an 0 8-bit input port port 9 8-bit input/output p9 7 / sck 1 output for free-running timers 2 and 3 port p9 6 / rxd 1 (ftoa 2 , ftoa 3 ), pwm timer output p9 5 / txd 1 (pw 1 , pw 2 , pw 3 ), serial communication p9 4 / sck 2 / interface (sci1 and sci2) input/output pw 3 (sck 1 , rxd 1 , txd 1 , sck 2 , rxd 2 , txd 2 ), p9 3 / rxd 2 / and 8-bit input/output port pw 2 p9 2 / txd 2 / pw 1 p9 1 / ftoa 3 p9 0 / ftoa 2 143
9.2 port 1 9.2.1 overview port 1 is an 8-bit input/output port with the pin configuration shown in figure 9-1. all pins have dual functions, except that in the single-chip mode pins 4, 3, and 2 do not have the wait, breq, and back functions (because the cpu does not access an external bus). outputs from port 1 can drive one ttl load and a 90 pf capacitive load. they can also drive a darlington transistor pair. 9.2.2 port 1 registers register configuration: table 9-2 lists the registers of port 1. table 9-2 port 1 registers name abbreviation read/write initial value address port 1 data direction register p1ddr w h'03 h'fe80 port 1 data register p1dr r/w * 1 undetermined * 2 h'fe82 system control register 1 syscr1 r/w h'87 h'fefc * 1 bits 1 and 0 are read-only. * 2 bits 1 and 0 are undetermined. other bits are initialized to 0. pin expanded modes single-chip mode p1 7 / tmo p1 7 (input/output) / tmo (output) p1 7 (input/output) / tmo (output) p1 6 / irq 1 / p1 6 (input/output) / irq 1 (input) / p1 6 (input/output) / irq 1 (input) / adtrg adtrg (input) adtrg (input) p1 5 / irq 0 p1 5 (input/output) / irq 0 (input) p1 5 (input/output) / irq 0 (input) port p1 4 / wait p1 4 (input/output) / wait (input) p1 4 (input/output) 1 p1 3 / breq p1 3 (input/output) / breq (input) p1 3 (input/output) p1 2 / back p1 2 (input/output) / back (output) p1 2 (input/output) p1 1 / e p1 1 (input) / e (output) p1 1 (input) / e (output) p1 0 / p1 0 (input) / ?(output) p1 0 (input) / ?(output) figure 9-1 pin functions of port 1 144
1. port 1 data direction register (p1ddr)?'fe80 p1ddr is an 8-bit register that selects the direction of each pin in port 1. a pin functions as an output pin if the corresponding bit in p1ddr is set to 1, and as an input pin if the bit is cleared to 0. p1ddr can be written but not read. an attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. a reset initializes p1ddr to h'03, so that pins p1 1 and p1 0 carry clock outputs and the other pins are set for input. in the hardware standby mode, p1ddr is cleared to h'00, stopping the clock outputs. p1ddr is not initialized in the software standby mode, so if a p1ddr bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 1 data register (or the ?or e clock). 2. port 1 data register (p1dr)?'fe82 p1dr is an 8-bit register containing the data for pins p1 7 to p1 0 . when the cpu reads p1dr, for output pins it reads the value in the p1dr latch, but for input pins, it obtains the pin status directly. note that when pins p1 1 and p1 0 are used for output, they output the clock signals (?and e), not the contents of p1dr. if the cpu reads pl 1 and pl 0 (when pl 1 ddr = pl 0 ddr = 1), it obtains the clock values at the current instant. 3. system control register 1 (syscr1)?'fefc bit 7 6 5 4 3 2 1 0 p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr initial value 0 0 0 0 0 0 1 1 read/write w w w w w w w w bit 7 6 5 4 3 2 1 0 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 initial value 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r r bit 7 6 5 4 3 2 1 0 irq 1 e irq 0 e nmieg brle initial value 1 0 0 0 0 1 1 1 read/write r/w r/w r/w r/w 145
syscr1 selects the functions of four of the port 1 pins. it also selects the input edge of the nmi pin. at a reset and in the hardware standby mode, syscr1 is initialized to h'87. it is not initialized in the software standby mode. bit 7?eserved: this bit cannot be modified and is always read as 1. bit 6?nterrupt request 1 enable (irq 1 e): this bit selects the function of pin p1 6 . bit 6 irq 1 e description 0 p1 6 functions as an input/output pin. (initial value) 1 p1 6 functions as the irq 1 input pin, regardless of the value set in p1 6 ddr. (however, the cpu can still read the pin status by reading p1dr.) bit 5?nterrupt request 0 enable (irq 0 e): this bit selects the function of pin p1 5 . bit 5 irq 0 e description 0 p1 5 functions as an input/output pin. (initial value) 1 p1 5 functions as the irq 0 input pin, regardless of the value set in p1 5 ddr. (however, the cpu can still read the pin status by reading p1dr.) bit 4?onmaskable interrupt edge (nmieg): this bit selects the input edge of the nmi pin. it is not related to port 0. bit 4 nmieg description 0 a nonmaskable interrupt is generated on the falling edge (initial value) of the input at the nmi pin. 1 a nonmaskable interrupt is generated on the rising edge of the input at the nmi pin. bit 3?us release enable (brle): this bit selects the functions of pins p1 2 and p1 3 . it is valid only in the expanded modes (modes 1, 2, 3, and 4). in the single-chip mode, pins p1 2 and p1 3 function as input/output pins regardless of the value of the brle bit. 146
bit 3 brle description 0 p1 3 and p1 2 function as input/output pins. (initial value) 1 p1 3 functions as the breq input pin. p1 2 functions as the back output pin. bits 2 to 0?eserved: these bits cannot be modified and are always read as 1. 9.2.3 pin functions in each mode port 1 operates differently in the expanded modes (modes 1, 2, 3, and 4) and the single-chip mode (mode 7). table 9-3 explains how the pin functions are selected in the expanded mode. table 9-4 explains how the pin functions are selected in the single-chip mode. table 9-3 port 1 pin functions in expanded modes pin selection of pin functions p1 7 / tmo the function depends on output select bits 3 to 0 (os3 to os0) of the 8-bit timer control/status register (tcsr) and on the p1 7 ddr bit as follows: os3 to os0 all four bits are 0 at least one bit is 1 p1 7 ddr 0 1 0 1 pin function p1 7 input p1 7 output tmo output p1 6 / irq 1 / the function depends on the irq 1 e bit and the trigger enable bit (trge) adtrg in the a/d control register (adcr) as follows: irq 1 e 0 1 trge 0 1 0 1 pin function p1 6 input/ adtrg irq 1 input irq 1 and output input adtrg input when used for p1 6 input/output, the input or output function is selected by p1 6 ddr. p1 5 / irq 0 the function depends on the irq 0 e bit and the p1 5 ddr bit as follows: irq 0 e 0 1 p1 5 ddr 0 1 0 1 pin function p1 5 input p1 5 output irq 0 input 147
table 9-3 port 1 pin functions in expanded modes (cont) pin selection of pin functions p1 4 / wait the function depends on the wait mode select 1 bit (wms1) of the wait-state control register (wcr) and the p1 4 ddr bit as follows: wms1 0 1 p1 4 ddr 0 1 0 1 pin function p1 4 input p1 4 output wait input p1 3 / breq the function depends on the brle bit and the p1 3 ddr bit as follows: brle 0 1 p1 3 ddr 0 1 0 1 pin function p1 3 input p1 3 output breq input p1 2 / back the function depends on the brle bit and the p1 2 ddr bit as follows: brle 0 1 p1 2 ddr 0 1 0 1 pin function p1 2 input p1 2 output back output p1 1 / e p1 1 ddr 0 1 pin function input e clock output p1 0 / p1 0 ddr 0 1 pin function input ?clock output 148
table 9-4 port 1 pin functions in single-chip modes pin selection of pin functions p1 7 / tmo the function depends on output select bits 3 to 0 (os3 to os0) of the 8-bit timer control/status register (tcsr) and on the p1 7 ddr bit as follows: os3 to os0 all four bits are 0 at least one bit is 1 p1 7 ddr 0 1 0 1 pin function p1 7 input p1 7 output tmo output p1 6 / irq 1 the function depends on the irq 1 e bit and the trigger enable bit (trge) / adtrg in the a/d control register (adcr) as follows: irq 1 e 0 1 trge 0 1 0 1 pin function p1 6 input/ adtrg irq 1 input irq 1 and output input adtrg input when used for p1 6 input/output, the input or output function is selected by p1 6 ddr. p1 5 / irq 0 the function depends on the irq 0 e bit and the p1 5 ddr bit as follows: irq 0 e 0 1 p1 5 ddr 0 1 0 1 pin function p1 5 input p1 5 output irq 0 input p1 4 p1 4 ddr 0 1 pin function input output p1 3 p1 3 ddr 0 1 pin function input output 149
table 9-4 port 1 pin functions in single-chip modes (cont) pin selection of pin functions p1 2 p1 2 ddr 0 1 pin function input output p1 1 / e p1 1 ddr 0 1 pin function input e clock output p1 0 / p1 0 ddr 0 1 pin function input ?clock output 9.3 port 2 9.3.1 overview port 2 is a five-bit input/output port with the pin configuration shown in figure 9-2. it functions as an input/output port only in the single-chip mode. in the expanded modes it is used for output of bus control signals. outputs from port 2 can drive one ttl load and a 90 pf capacitive load. they can also drive a darlington transistor pair. pin expanded modes single-chip mode p2 4 / wr wr (output) p2 4 (input/output) port p2 3 / rd rd (output) p2 3 (input/output) 2 p2 2 / ds ds (output) p2 2 (input/output) p2 1 / r/w r/w (output) p2 1 (input/output) p2 0 / as as (output) p2 0 (input/output) figure 9-2 pin functions of port 2 150
9.3.2 port 2 registers register configuration: table 9-5 lists the registers of port 2. table 9-5 port 2 registers name abbreviation read/write initial value address port 2 data direction register p2ddr w h'e0 h'fe81 port 2 data register p2dr r/w h'e0 h'fe83 1. port 2 data direction register (p2ddr)?'fe81 p2ddr is an 8-bit register that selects the direction of each pin in port 2. single-chip mode: a pin functions as an output pin if the corresponding bit in p2ddr is set to 1, and as an input pin if the bit is cleared to 0. bits 4 to 0 can be written but not read. an attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. bits 7 to 5 are reserved. they cannot be modified and are always read as 1. at a reset and in the hardware standby mode, p2ddr is initialized to h'e0, making all five pins input pins. p2ddr is not initialized in the software standby mode, so if a p2ddr bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 2 data register. expanded modes: all bits of p2ddr are fixed at 1 and cannot be modified. bit 7 6 5 4 3 2 1 0 p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr initial value 1 1 1 0 0 0 0 0 read/write w w w w w 151
2. port 2 data register (p2dr)?'fe83 p2dr is an 8-bit register containing the data for pins p2 4 to p2 0 . bits 7 to 5 are reserved. they cannot be modified and are always read as 1. when the cpu reads p2dr, for output pins it reads the value in the p2dr latch, but for input pins, it obtains the pin status directly. 9.3.3 pin functions in each mode port 2 has different functions in the expanded modes (modes 1, 2, 3, 4) and the single-chip mode (mode 7). separate descriptions are given below. pin functions in expanded modes: in the expanded modes (modes 1, 2, 3, and 4), all pins of p2ddr is automatically set to 1 for output. port 2 outputs the bus control signals (as, r/w, ds, rd, wr). figure 9-3 shows the pin functions in the expanded modes. bit 7 6 5 4 3 2 1 0 p2 4 p2 3 p2 2 p2 1 p2 0 initial value 1 1 1 0 0 0 0 0 read/write r/w r/w r/w r/w r/w wr (output) port rd (output) 2 ds (output) r/w (output) as (output) figure 9-3 port 2 pin functions in expanded modes 152
pin functions in single-chip mode: in the single-chip mode (mode 7), each of the port 2 pins can be designated as an input pin or an output pin, as indicated in figure 9-4, by setting the corresponding bit in p2ddr to 1 for output or clearing it to 0 for input. 9.4 port 3 9.4.1 overview port 3 is an 8-bit input/output port with the pin configuration shown in figure 9-5. in the expanded modes it operates as the external data bus (d 7 ?d 0 ). in the single-chip mode it operates as a general-purpose input/output port. outputs from port 3 can drive one ttl load and a 90pf capacitive load. they can also drive a darlington transistor pair. p2 4 (input/output) port p2 3 (input/output) 2 p2 2 (input/output) p2 1 (input/output) p2 0 (input/output) pin expanded modes single-chip mode p3 7 / d 7 d 7 (input/output) p3 7 (input/output) p3 6 / d 6 d 6 (input/output) p3 6 (input/output) p3 5 / d 5 d 5 (input/output) p3 5 (input/output) port p3 4 / d 4 d 4 (input/output) p3 4 (input/output) 3 p3 3 / d 3 d 3 (input/output) p3 3 (input/output) p3 2 / d 2 d 2 (input/output) p3 2 (input/output) p3 1 / d 1 d 1 (input/output) p3 1 (input/output) p3 0 / d 0 d 0 (input/output) p3 0 (input/output) figure 9-4 port 2 pin functions in single-chip mode figure 9-5 pin functions of port 3 153
9.4.2 port 3 registers register configuration: table 9-6 lists the registers of port 3. table 9-6 port 3 registers name abbreviation read/write initial value address port 3 data direction register p3ddr w h'00 h'fe84 port 3 data register p3dr r/w h'00 h'fe86 1. port 3 data direction register (p3ddr)?'fe84 p3ddr is an 8-bit register that selects the direction of each pin in port 3. single-chip mode: a pin functions as an output pin if the corresponding bit in p3ddr is set to 1, and as an input pin if the bit is cleared to 0. p3ddr can be written but not read. an attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. at a reset and in the hardware standby mode, p3ddr is initialized to h'00, making all eight pins input pins. p3ddr is not initialized in the software standby mode, so if a p3ddr bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 3 data register. expanded modes: p3ddr is not used. bit 7 6 5 4 3 2 1 0 p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w 154
2. port 3 data register (p3dr)?'fe86 p3dr is an 8-bit register containing the data for pins p3 7 to p3 0 . at a reset and in the hardware standby mode, p3dr is initialized to h'00. when the cpu reads p3dr, for output pins it reads the value in the p3dr latch, but for input pins, it obtains the pin status directly. 9.4.3 pin functions in each mode port 3 has different functions in the expanded modes (modes 1, 2, 3, 4) and the single-chip mode (mode 7). separate descriptions are given below. pin functions in expanded modes: in the expanded modes (modes 1, 2, 3, and 4), port 3 is automatically used as the data bus and p3ddr is ignored. figure 9-6 shows the pin functions for the expanded modes. bit 7 6 5 4 3 2 1 0 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w d 7 (input/output) d 6 (input/output) d 5 (input/output) port d 4 (input/output) 3 d 3 (input/output) d 2 (input/output) d 1 (input/output) d 0 (input/output) figure 9-6 port 3 pin functions in expanded modes 155
pin functions in single-chip mode: in the single-chip mode (mode 7), each of the port 3 pins can be designated as an input pin or an output pin, as indicated in figure 9-7, by setting the corresponding bit in p3ddr to 1 for output or clearing it to 0 for input. 9.5 port 4 9.5.1 overview port 4 is an 8-bit input/output port with the pin configuration shown in figure 9-8. in the expanded modes it provides the low bits (a 7 ?a 0 ) of the address bus. in the single-chip mode it operates as a general-purpose input/output port. outputs from port 4 can drive one ttl load and a 90 pf capacitive load. they can also drive a darlington transistor pair or led (with 10 ma current sink). p3 7 (input/output) p3 6 (input/output) p3 5 (input/output) port p3 4 (input/output) 3 p3 3 (input/output) p3 2 (input/output) p3 1 (input/output) p3 0 (input/output) pin expanded modes single-chip mode p4 7 / a 7 a 7 (output) p4 7 (input/output) p4 6 / a 6 a 6 (output) p4 6 (input/output) p4 5 / a 5 a 5 (output) p4 5 (input/output) port p4 4 / a 4 a 4 (output) p4 4 (input/output) 4 p4 3 / a 3 a 3 (output) p4 3 (input/output) p4 2 / a 2 a 2 (output) p4 2 (input/output) p4 1 / a 1 a 1 (output) p4 1 (input/output) p4 0 / a 0 a 0 (output) p4 0 (input/output) figure 9-7 port 3 pin functions in single-chip mode figure 9-8 pin functions of port 4 156
9.5.2 port 4 registers register configuration: table 9-7 lists the registers of port 4. table 9-7 port 4 registers name abbreviation read/write initial value address port 4 data direction register p4ddr w h'00 h'fe85 port 4 data register p4dr r/w h'00 h'fe87 1. port 4 data direction register (p4ddr)?'fe85 p4ddr is an 8-bit register that selects the direction of each pin in port 4. single-chip mode: a pin functions as an output pin if the corresponding bit in p4ddr is set to 1, and as in input pin if the bit is cleared to 0. p4ddr can be written but not read. an attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. at a reset and in the hardware standby mode, p4ddr is initialized to h'00, making all eight pins input pins. p4ddr is not initialized in the software standby mode, so if a p4ddr bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 4 data register. expanded modes: all bits of p4ddr are fixed at 1 and cannot be modified. bit 7 6 5 4 3 2 1 0 p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w 157
2. port 4 data register (p4dr)?'fe87 p4dr is an 8-bit register containing the data for pins p4 7 to p4 0 . at a reset and in the hardware standby mode, p4dr is initialized to h'00. when the cpu reads p4dr, for output pins it reads the value in the p4dr latch, but for input pins, it obtains the pin status directly. 9.5.3 pin functions in each mode port 4 has different functions in the expanded modes (modes 1, 2, 3, 4) and the single-chip mode (mode 7). separate descriptions are given below. pin functions in expanded modes: in the expanded modes (modes 1, 2, 3, and 4), port 4 is used for output of the low bits (a 7 ?a 0 ) of the address bus. p4ddr is automatically set for output. figure 9-9 shows the pin functions for the expanded modes. pin functions in single-chip mode: in the single-chip mode (mode 7), each of the port 4 pins can be designated as an input pin or an output pin, as indicated in figure 9-10, by setting the corresponding bit in p4ddr to 1 for output or clearing it to 0 for input. bit 7 6 5 4 3 2 1 0 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w a 7 (output) a 6 (output) a 5 (output) port a 4 (output) 4 a 3 (output) a 2 (output) a 1 (output) a 0 (output) figure 9-9 port 4 pin functions in expanded modes 158
9.6 port 5 9.6.1 overview port 5 is an 8-bit input/output port with the pin configuration shown in figure 9-11. in the expanded modes that use the on-chip rom (modes 2 and 4), the pins of port 5 function either as general-purpose input pins or as bits a 15 ?a 8 of the address bus, depending on the port 5 data direction register (p5ddr). port 5 has built-in mos pull-ups that can be turned on or off under program control. outputs from port 5 can drive one ttl load and a 90 pf capacitive load. they can also drive a darlington transistor pair. p4 7 (input/output) p4 6 (input/output) p4 5 (input/output) port p4 4 (input/output) 4 p4 3 (input/output) p4 2 (input/output) p4 1 (input/output) p4 0 (input/output) pin modes 1 and 3 modes 2 and 4 single-chip mode p5 7 / a 15 a 15 (output) p5 7 (input) / a 15 (output) p5 7 (input/output) p5 6 / a 14 a 14 (output) p5 6 (input) / a 14 (output) p5 6 (input/output) p5 5 / a 13 a 13 (output) p5 5 (input) / a 13 (output) p5 5 (input/output) port p5 4 / a 12 a 12 (output) p5 4 (input) / a 12 (output) p5 4 (input/output) 5 p5 3 / a 11 a 11 (output) p5 3 (input) / a 11 (output) p5 3 (input/output) p5 2 / a 10 a 10 (output) p5 2 (input) / a 10 (output) p5 2 (input/output) p5 1 / a 9 a 9 (output) p5 1 (input) / a 9 (output) p5 1 (input/output) p5 0 / a 8 a 8 (output) p5 0 (input) / a 8 (output) p5 0 (input/output) figure 9-10 port 4 pin functions in single-chip mode figure 9-11 pin functions of port 5 159
9.6.2 port 5 registers register configuration: table 9-8 lists the registers of port 5. table 9-8 port 5 registers name abbreviation read/write initial value address port 5 data direction register p5ddr w h'00 h'fe88 port 5 data register p5dr r/w h'00 h'fe8a 1. port 5 data direction register (p5ddr)?'fe88 p5ddr is an 8-bit register that selects the direction of each pin in port 5. single-chip mode: a pin functions as an output pin if the corresponding bit in p5ddr is set to 1, and as an input pin if the bit is cleared to 0. p5ddr can be written but not read. an attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. at a reset and in the hardware standby mode, p5ddr is initialized to h'00, making all eight pins input pins. p5ddr is not initialized in the software standby mode, so if a p5ddr bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 5 data register. expanded modes using on-chip rom (modes 2 and 4): if a 1 is set in p5ddr, the corresponding pin is used for address output. if a 0 is set in p5ddr, the pin is used for general- purpose input. p5ddr is initialized to h'00 at a reset and in the hardware standby mode. expanded modes not using on-chip rom (modes 1 and 3): all bits of p5ddr are fixed at 1 and cannot be modified. port 5 is used for address output. bit 7 6 5 4 3 2 1 0 p5 7 ddr p5 6 ddr p5 5 ddr p5 4 ddr p5 3 ddr p5 2 ddr p5 1 ddr p5 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w 160
port 5 data register (p5dr)?'fe8a p5dr is an 8-bit register containing the data for pins p5 7 to p5 0 . at a reset and in the hardware standby mode, p5dr is initialized to h'00. when the cpu reads p5dr, for output pins it reads the value in the p5dr latch, but for input pins, it obtains the pin status directly. 9.6.3 pin functions in each mode port 5 operates in one way in modes 1 and 3, in another way in modes 2 and 4, and in a third way in mode 7. separate descriptions are given below. pin functions in modes 1 and 3: in modes 1 and 3 (expanded modes in which the on-chip rom is not used), all bits of p5ddr are automatically set to 1 for output, and the pins of port 5 carry bits a 15 ?a 8 of the address bus. figure 9-12 shows the pin functions for modes 1 and 3. bit 7 6 5 4 3 2 1 0 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w a 15 (output) a 14 (output) a 13 (output) port a 12 (output) 5 a 11 (output) a 10 (output) a 9 (output) a 8 (output) figure 9-12 port 5 pin functions in modes 1 and 3 161
pin functions in modes 2 and 4: in modes 2 and 4, (expanded modes in which the on-chip rom is used), software can select whether to use port 5 for general-purpose input, or for output of bits a 15 ?a 8 of the address bus. if a bit in p5ddr is set to 1, the corresponding pin is used for address output. if the bit is cleared to 0, the pin is used for input. a reset clears all p5ddr bits to 0, so before the address bus is used, all necessary bits in p5ddr must be set to 1. figure 9-13 shows the pin functions in modes 2 and 4. pin functions in single-chip mode: in the single-chip mode (mode 7), each of the port 5 pins can be designated as an input pin or an output pin, as indicated in figure 9-14, by setting the corresponding bit in p5ddr to 1 for output or clearing it to 0 for input. when p5ddr when p5ddr bit bit is set to ? is cleared to ? a 15 (output) p5 7 (input) a 14 (output) p5 6 (input) a 13 (output) p5 5 (input) port a 12 (output) p5 4 (input) 5 a 11 (output) p5 3 (input) a 10 (output) p5 2 (input) a 9 (output) p5 1 (input) a 8 (output) p5 0 (input) p5 7 (input/output) p5 6 (input/output) p5 5 (input/output) port p5 4 (input/output) 5 p5 3 (input/output) p5 2 (input/output) p5 1 (input/output) p5 0 (input/output) figure 9-13 port 5 pin functions in modes 2 and 4 figure 9-14 port 5 pin functions in single-chip mode 162
9.6.4 built-in mos pull-up the mos input pull-ups of port 5 are turned on by clearing the corresponding bit in p5ddr to 0 and writing a 1 in p5dr. these pull-ups are turned off at a reset and in the hardware standby mode. table 9-9 indicates the status of the mos pull-ups in various modes. table 9-9 status of mos pull-ups for port 5 mode reset hardware standby mode other operating states * 1 off off off 2 on/off 3 off 4 7 * including the software standby mode. notation: off: the mos pull-up is always off. on/off: the mos pull-up is on when p5ddr = 0 and p5dr = 1, and off otherwise. note on usage of mos pull-ups if the bit manipulation instructions listed below are executed on input/output ports 5 and 6 which have selectable mos pull-ups, the logic levels at input pins will be transferred to the dr latches, causing the mos pull-ups to be unintentionally switched on or off. this can occur with the following bit manipulation instructions: bset, bclr, bnot (1) specific example (bset instruction): an example will be shown in which the bset instruction is executed for port 5 under the following conditions: p5 7 : input pin, low, mos pull-up transistor on p5 6 : input pin, high, mos pull-up transistor off p5 5 ?p5 0 : output pins, low the intended purpose of this bset instruction is to switch the output level at p5 0 from low to high. on/off 163
164 a: before execution of bset instruction p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 input/output input input output output output output output output pin state low high low low low low low low ddr 0 0 1 1 1 1 1 1 dr 1 0 0 0 0 0 0 0 pull-up on off off off off off off off b: execution of bset instruction bset.b #0 @port5 ;set bit 0 in data register c: after execution of bset instruction p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 input/output input input output output output output output output pin state low high low low low low low high ddr 0 0 1 1 1 1 1 1 dr 0 1 0 0 0 0 0 1 pull-up off on off off off off off off explanation: to execute the bset instruction, the cpu begins by reading port 5. since p5 7 and p5 6 are input pins, the cpu reads the level of these pins directly, not the value in the data register. it reads p5 7 as low (0) and p5 6 as high (1). since p5 5 to p5 0 are output pins, for these pins the cpu reads the value in the data register (0). the cpu therefore reads the value of port 5 as h'40, although the actual value in p5dr is h'80. next the cpu sets bit 0 of the read data to 1, changing the value to h'41. finally, the cpu writes this value (h'41) back to p5dr to complete the bset instruction. as a result, bit p5 0 is set to 1, switching pin p5 0 to high output. in addition, bits p5 7 and p5 6 are both modified, changing the on/off settings of the mos pull-up transistors of pins p5 7 and p5 6 . programming solution: the switching of the pull-ups for p5 7 and p5 6 in the preceding example can be avoided by using a byte in ram as a work area for p5dr, performing bit manipulations on the work area, then writing the result to p5dr.
a: before execution of bset instruction mov.b #80, r0 ;write data (h'80) for data register mov.b r0, @ram0 ;write to work area (ram0) mov.b r0, @port5 ;write to p5dr p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 input/output input input output output output output output output pin state low high low low low low low low ddr 0 0 1 1 1 1 1 1 dr 1 0 0 0 0 0 0 0 pull-up on off off off off off off off ram0 1 0 0 0 0 0 0 0 b: execution of bset instruction bset.b #0, @ram0 ;set bit 0 in work area (ram0) c: after execution of bset instruction mov.b @ram0, r0 ;get value in work area (ram0) mov.b r0, @port5 ;write value to p5dr p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 input/output input input output output output output output output pin state low high low low low low low high ddr 0 0 1 1 1 1 1 1 dr 1 0 0 0 0 0 0 1 pull-up on off off off off off off off ram0 1 0 0 0 0 0 0 0 9.7 port 6 9.7.1 overview port 6 is a 4-bit input/output port with the pin configuration shown in figure 9-15. in modes 7, 2, and 1, port 6 is used for irq 2 to irq 5 input and pwm timer output. in mode 4, port 6 is used for irq 2 to irq 5 input and page address output. in mode 3, port 6 is used for page address output. port 6 has built-in mos pull-ups that can be turned on or off under program control. outputs from port 6 can drive one ttl load and a 90 pf capacitive load. they can also drive a darlington transistor pair. 165
9.7.2 port 6 registers register configuration: table 9-10 lists the registers of port 6. table 9-10 port 6 registers name abbreviation read/write initial value address port 6 data direction register p6ddr w h'f0 h'fe89 port 6 data register p6dr r/w h'f0 h'fe8b system control register 2 syscr2 r/w h'80 h'fefd 1. port 6 data direction register (p6ddr)?'fe89 p6ddr is an 8-bit register that selects the direction of each pin in port 6. single-chip mode and expanded minimum modes: a pin functions as an output pin if the corresponding bit in p6ddr is set to 1, and as in input pin if the bit is cleared to 0. bits 7 to 4 are reserved. they cannot be modified and are always read as 1. pin mode 3 mode 4 mode 1 and 2 and single-chip mode p6 3 / pw 3 / a 19 (output) p6 3 (input) / irq 5 (input) / p6 3 (input/output) / irq 5 / a 19 a 19 (output) irq 5 (input) / pw 3 (output) p6 2 / pw 2 / a 18 (output) p6 2 (input) / irq 4 (input) / p6 2 (input/output) / port irq 4 / a 18 a 18 (output) irq 4 (input) / 6 pw 2 (output) p6 1 / pw 1 / a 17 (output) p6 1 (input) / irq 3 (input) / p6 1 (input/output) / irq 3 / a 17 a 17 (output) irq 3 (input) / pw 1 (output) p6 0 / irq 2 / a 16 (output) p6 0 (input) / irq 2 (input) / p6 0 (input/output) / a 16 a 16 (output) irq 2 (input) bit 7 6 5 4 3 2 1 0 p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr initial value 1 1 1 1 0 0 0 0 read/write w w w w figure 9-15 pin functions of port 6 166
bits 3 to 0 can be written but not read. an attempt to read these bits does not cause an error, but all bits are read as 1, regardless of their true values. at a reset and in the hardware standby mode, p6ddr is initialized to h'f0, making all four pins input pins. p6ddr is not initialized in the software standby mode. in the single-chip mode, if a p6ddr bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 6 data register. expanded maximum mode using on-chip rom (mode 4): if a 1 is set in p6ddr, the corresponding pin is used for address output. if a 0 is set in p6ddr, the pin is used for input. p6ddr is initialized to h'f0 at a reset and in the hardware standby mode. expanded maximum mode not using on-chip rom (mode 3): all bits of p6ddr are fixed at 1 and cannot be modified. 2. port 6 data register (p6dr)?'fe8b p6dr is an 8-bit register containing data for pins p6 3 to p6 0 . bits 7 to 4 are reserved. they cannot be modified and are always read as 1. at a reset and in the hardware standby mode, p6dr is initialized to h'f0. when the cpu reads p6dr, for output pins it reads the value in the p6dr latch, but for input pins, it obtains the pin status directly. 3. system control register 2 (syscr2)?'fefd bit 7 6 5 4 3 2 1 0 p6 3 p6 2 p6 1 p6 0 initial value 1 1 1 1 0 0 0 0 read/write r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 irq 5 e irq 4 e irq 3 e irq 2 e p6pwme p9pwme p9sci2e initial value 1 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w 167
syscr2 controls the functions of port 6 and the functions of some pins in port 9. syscr2 is initialized to h'80 by a reset and in the hardware standby mode. it is not initialized in the software standby mode. bit 7?eserved: this bit cannot be modified and is always read as 1. bit 6?nterrupt request 5 enable (irq 5 e): selects the function of pin p6 3 . bit 6 irq 5 e description 0 p6 3 functions as an input/output pin (but as the pw3 output pin (initial value) if p6pwme and the oe bit of pwm timer 3 are both set to 1). 1 p6 3 is the irq 5 input pin regardless of the value of p6 3 ddr (although the logic level of the pin can still be read). bit 5?nterrupt request 4 enable (irq 4 e): selects the function of pin p6 2 . bit 5 irq 4 e description 0 p6 2 functions as an input/output pin (but as the pw2 output (initial value) pin if p6pwme and the oe bit of pwm timer 2 are both set to 1). 1 p6 2 is the irq 4 input pin regardless of the value of p6 2 ddr (although the logic level of the pin can still be read). bit 4?nterrupt request 3 enable (irq 3 e): selects the function of pin p6 1 . bit 4 irq 3 e description 0 p6 1 functions as an input/output pin (but as the pw1 output (initial value) pin if p6pwme and the oe bit of pwm timer 1 are both set to 1). 1 p6 1 is the irq 3 input pin regardless of the value of p6 1 ddr (although the logic level of the pin can still be read). bit 3?nterrupt request 2 enable (irq 2 e): selects the function of pin p6 0 . bit 3 irq 2 e description 0 p6 0 functions as an input/output pin. (initial value) 1 p6 0 is the irq 2 input pin regardless of the value of p6 0 ddr (although the logic level of the pin can still be read). 168
bit 2?ort 6 pwm enable (p6pwme): controls pin functions of port 6. bit 2 p6pwme description 0 p6 3 to p6 1 function as input/output pins (initial value) (or as irq input pins when bits irq5e to irq3e are set to 1). 1 p6 3 to p6 1 function as pwm output pins if the corresponding oe bit of pwm3 to pwm1 is set to 1. if the oe bit is cleared to 0 or the irqe bit is set to 1, the pin functions as an input/output pin. bit 1?ort 9 pwm enable (p9pwme): controls pin functions of port 9. bit 1 p9pwme description 0 the pwm functions of p9 4 to p9 2 are disabled. (initial value) (see section 9.10.3, ?in functions.) 1 the pwm functions of p9 4 to p9 2 are enabled. (see section 9.10.3, ?in functions.? bit 0?ort 9 sci2 enable (p9pwme): controls pin functions of port 9. bit 1 p9sci2e description 0 the serial communication interface functions of p9 4 to p9 2 (initial value) are disabled. (see section 9.10.3, ?in functions.? 1 the serial communication interface functions of p94 to p92 are enabled. (see section 9.10.3, ?in functions.? 169
9.7.3 pin functions in each mode the usage of port 6 depends on the mcu operating mode. separate descriptions are given below. pin functions in mode 3: in mode 3 (the expanded maximum mode in which the on-chip rom is not used), p6ddr is automatically set for output, and the pins of port 6 carry the page address bits (a 19 ?a 16 ) of the address bus. figure 9-16 shows the pin functions for mode 3. pin functions in mode 4: in mode 4, (the expanded maximum mode in which the on-chip rom is used), software can select whether to use port 6 for general-purpose input, irq 2 to irq 5 input, or output of page address bits. if a bit in p6ddr is set to 1, the corresponding pin is used for page address output. if the p6ddr bit is cleared to 0 and the corresponding irqne bit is cleared to 0, the pin is used for general- purpose input. if the p6ddr bit is cleared to 0 and the corresponding irqne bit is set to 1, the pin is used for irq 2 to irq 5 input. a reset initializes these pins to the general-purpose input function, so when the address bus is used, all necessary bits in p6ddr must first be set to 1. figure 9-17 shows the pin functions in mode 4. pin functions in single-chip mode and expanded minimum modes: in the single-chip mode (mode 7) and expanded minimum modes (modes 1 and 2), the port 6 pins can be designated individually as input or output pins. port 6 can be used for general-purpose input/output, irq input, or pwm output, depending on the combination of settings of the irqe and p6pwme bits in system control register 2 and the oe a 19 (output) port a 18 (output) 6 a 17 (output) a 16 (output) figure 9-16 port 6 pin functions in mode 3 when p6ddr bit when p6ddr bit is cleared to 0 is set to 1 irqne = 0 irqne = 1 a 19 (output) p6 3 (input) irq 5 port a 18 (output) p6 2 (input) irq 4 6 a 17 (output) p6 1 (input) irq 3 a 16 (output) p6 0 (input) irq 2 figure 9-17 port 6 pin functions in mode 4 170
bits of the three pwm timers. figure 9-18 shows the pin functions in modes 7, 2, and 1. table 9-11 port 6 pin functions in modes 7, 2, and 1 pin selection of pin functions p6 3 / irq 5 / the function depends on the interrupt request 5 enable bit (irq 5 e) and port 6 pwm pw 3 enable bit (p6pwme) in system control register 2 (syscr2), and the output enable bit (oe) of pwm timer 3. irq 5 e 0 1 p6pwme 0 1 0 1 oe 0 1 0 1 0 1 0 1 pin function p6 3 input/output pw 3 output irq 5 input irq 5 input when used for p6 3 input/output, the input or output function is selected by p6 3 ddr. p6 2 / irq 4 / the function depends on the interrupt request 4 enable bit (irq 4 e) and p6pwme pw 2 bit in syscr2, and the oe bit of pwm timer 2. irq 4 e 0 1 p6pwme 0 1 0 1 oe 0 1 0 1 0 1 0 1 pin function p6 2 input/output pw 2 output irq 4 input irq 4 input when used for p6 2 input/output, the input or output function is selected by p6 2 ddr. p6 3 (input/output) / irq 5 / pw 3 port p6 2 (input/output) / irq 4 / pw 2 6 p6 1 (input/output) / irq 3 / pw 1 p6 0 (input/output) / irq 2 figure 9-18 port 6 pin functions in modes 7, 2, and 1 171
table 9-11 port 6 pin functions in modes 7, 2, and 1 (cont) pin selection of pin functions p6 1 / irq 3 / the function depends on the interrupt request 3 enable bit (irq 3 e) and p6pwme pw 1 bit in syscr2, and the oe bit of pwm timer 1. irq 3 e 0 1 p6pwme 0 1 0 1 oe 0 1 0 1 0 1 0 1 pin function p6 1 input/output pw 1 output irq 3 input irq 3 input when used for p6 1 input/output, the input or output function is selected by p6 1 ddr. p6 0 / irq 2 the function depends on the interrupt request 2 enable bit (irq 2 e) in syscr2. irq 2 e 0 1 pin function p6 0 input/output irq 2 input when used for p6 0 input/output, the input or output function is selected by p6 0 ddr. 9.7.4 built-in mos pull-up port 6 has programmable mos input pull-ups which are turned on by clearing the corresponding bit in p6ddr to 0 and writing a 1 in p6dr. these pull-ups are turned off at a reset and in the hardware standby mode. table 9-12 indicates the status of the mos pull-ups in various modes. table 9-12 status of mos pull-ups for port 5 mode reset hardware standby mode other operating states * 1 off off 2 3 off 4 7 * including software standby mode. notation: off: the mos pull-up is always off. on/off: the mos pull-up is on when p6ddr = 0 and p6dr = 1, and off otherwise. note: when p6 1 , p6 2 , and p6 3 are used for pwm timer output, their mos pull-ups are switched off regardless of the values in p6ddr and p6dr. on/off on/off 172
9.8 port 7 9.8.1 overview port 7 is an 8-bit input/output port with the pin configuration shown in figure 9-19. its pins also carry input and output signals for the on-chip free-running timers (frt1, frt2, and frt3), and two input signals for the on-chip 8-bit timer. port 7 has schmitt inputs. outputs from port 7 can drive one ttl load and a 30 pf capacitive load. they can also drive a darlington transistor pair. 9.8.2 port 7 registers register configuration: table 9-13 lists the registers of port 7. table 9-13 port 7 registers name abbreviation read/write initial value address port 7 data direction register p7ddr w h'00 h'fe8c port 7 data register p7dr r/w h'00 h'fe8e 1. port 7 data direction register (p7ddr)?'fe8c p7ddr is an 8-bit register that selects the direction of each pin in port 7. a pin functions as an output pin if the corresponding bit in p7ddr is set to 1, and as an input pin if the bit is cleared to 0. p7 7 (input/output) / ftoa 1 (output) p7 6 (input/output) / ftob 3 (output) / ftci 3 (input) p7 5 (input/output) / ftob 2 (output) / ftci 2 (input) port p7 4 (input/output) / ftob 1 (output) / ftci 1 (input) 7 p7 3 (input/output) / fti 3 (input) /tmri (input) p7 2 (input/output) / fti 2 (input) p7 1 (input/output) / fti 1 (input) p7 0 (input/output) / tmci (input) figure 9-19 pin functions of port 7 bit 7 6 5 4 3 2 1 0 p7 7 ddr p7 6 ddr p7 5 ddr p7 4 ddr p7 3 ddr p7 2 ddr p7 1 ddr p7 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w 173
p7ddr can be written but not read. an attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. at a reset and in the hardware standby mode, p7ddr is initialized to h'00, setting all pins for input. p7ddr is not initialized in the software standby mode, so if a p7ddr bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 7 data register. a transition to the software standby mode initializes the on-chip supporting modules, so any pins of port 7 that were being used by an on-chip timer when the transition occurs revert to general- purpose input or output, controlled by p7ddr and p7dr. 2. port 7 data register (p7dr)?'fe8e p7dr is an 8-bit register containing the data for pins p7 7 to p7 0 . when the cpu reads p7dr, for output pins it reads the value in the p7dr latch, but for input pins, it obtains the pin status directly. 9.8.3 pin functions the pin functions of port 7 are the same in all mcu operating modes. as figure 9-19 indicated, these pins are used for input and output of on-chip timer signals as well as for general-purpose input and output. for some pins, two or more functions can be enabled simultaneously. bit 7 6 5 4 3 2 1 0 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 174
table 9-14 shows how the functions of the pins of port 7 are selected. table 9-14 port 7 pin functions pin selection of pin functions p7 7 / the function depends on the output enable a bit (oea) of the frt1 timer control ftoa 1 register (tcr) and on the p7 7 ddr bit as follows: oea 0 1 p7 7 ddr 0 1 0 1 pin function p7 7 input p7 7 output ftoa 1 output p7 6 / the function depends on the output compare b bit (oeb) of the frt3 timer control ftob 3 / register (tcr) and on the p7 6 ddr bit as follows: ftci 3 oeb 0 1 p7 6 ddr 0 1 0 1 pin function p7 6 input p7 6 output ftob 3 output ftci 3 input p7 5 / the function depends on the output compare b bit (oeb) of the frt2 timer control ftob 2 / register (tcr) and on the p7 5 ddr bit as follows: ftci 2 oeb 0 1 p7 5 ddr 0 1 0 1 pin function p7 5 input p7 5 output ftob 2 output ftci 2 input p7 4 / the function depends on the output compare b bit (oeb) of the frt1 timer control ftob 1 / register (tcr) and on the p7 4 ddr bit as follows: ftci 1 oeb 0 1 p7 4 ddr 0 1 0 1 pin function p7 4 input p7 4 output ftob 1 output ftci 1 input 175
table 9-14 port 7 pin functions (cont) pin selection of pin functions p7 3 / fti 3 / the function depends on the counter clear bits 1 and 0 (cclr1 and cclr0) in the tmri timer control register (tcr) of the 8-bit timer, and on the p7 3 ddr bit as follows: the tmri function is operative when bits cclr0 and cclr1 in the timer control register (tcr) of the 8-bit timer are both set to 1. p7 3 ddr 0 1 pin function p7 3 input p7 3 output fti 3 input and tmri input p7 2 / fti 2 p7 2 ddr 0 1 pin function p7 2 input p7 2 output fti 2 input p7 1 / fti 1 p7 1 ddr 0 1 pin function p7 1 input p7 1 output fti 1 input p7 0 / tmci this pin always has a general-purpose input/output function, and can simultaneously be used for external clock input for the 8-bit timer, depending on clock select bits 2 to 0 (cks2, cks1, and cks0) in the timer control register (tcr). see section 11, ?-bit timer?for details. p7 0 ddr 0 1 pin function p7 0 input p7 0 output tmci input 176
9.9 port 8 9.9.1 overview port 8 is an 8-bit input port that also receives inputs for the on-chip a/d converter. the pin functions are the same in all mcu operating modes, as shown in figure 9-20. 9.9.2 port 8 registers register configuration: port 8 has only the data register described in table 9-15. since it is exclusively an input port, there is no data direction register. table 9-15 port 8 registers name abbreviation read/write address port 8 data register p8dr r h'fe8f 1. port 8 data register (p8dr)?'fe8f when the cpu reads p8dr it always reads the current status of each pin, except that during a/d conversion, the pin being used for analog input reads 1 regardless of the input voltage at that pin. p8 7 (input) / an 7 (input) p8 6 (input) / an 6 (input) p8 5 (input) / an 5 (input) port p8 4 (input) / an 4 (input) 8 p8 3 (input) / an 3 (input) p8 2 (input) / an 2 (input) p8 1 (input) / an 1 (input) p8 0 (input) / an 0 (input) figure 9-20 pin functions of port 8 bit 7 6 5 4 3 2 1 0 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r 177
9.10 port 9 9.10.1 overview port 9 is an 8-bit input/output port with the pin configuration shown in figure 9-21. in addition to general-purpose input and output, its pins are used for the output compare a signals from free- running timers 2 and 3, for pwm timer output, and for input and output by the on-chip serial communication interfaces (sci1 and sci2). the pin functions are the same in all mcu operating modes. outputs from port 9 can drive one ttl load and a 30 pf capacitive load. they can also drive a darlington transistor pair. 9.10.2 port 9 registers register configuration: table 9-16 lists the registers of port 9. table 9-16 port 9 registers name abbreviation read/write initial value address port 9 data direction register p9ddr w h'00 h'fefe port 9 data register p9dr r/w h'00 h'feff p9 7 (input/output) / sck 1 (input/output) p9 6 (input/output) / rxd 1 (input) p9 5 (input/output) / txd 1 (output) port p9 4 (input/output) / sck 2 (input/output) * / pw 3 (output) 9 p9 3 (input/output) / rxd 2 (input) * / pw 2 (output) p9 2 (input/output) / txd 2 (output) * / pw 1 (output) p9 1 (input/output) / ftoa 3 (output) p9 0 (input/output) / ftoa 2 (output) * the sci2 functions of p9 2 , p9 3 , and p9 4 cannot be combined with the pwm functions. figure 9-21 pin functions of port 9 178
1. port 9 data direction register (p9ddr)?'fefe p9ddr is an 8-bit register that selects the direction of each pin in port 9. a pin functions as an output pin if the corresponding bit in p9ddr is set to 1, and as an input pin if the bit is cleared to 0. p9ddr can be written but not read. an attempt to read this register does not cause an error, but all bits are read as 1, regardless of their true values. at a reset and in the hardware standby mode, p9ddr is initialized to h'00, setting all pins for input. p9ddr is not initialized in the software standby mode, so if a p9ddr bit is set to 1 when the chip enters the software standby mode, the corresponding pin continues to output the value in the port 9 data register. a transition to the software standby mode initializes the on-chip supporting modules, so any pins of port 9 that were being used by an on-chip module (example: free-running timer output) when the transition occurs revert to general-purpose input or output, controlled by p9ddr and p9dr. 2. port 9 data register (p9dr)?'feff p9dr is an 8-bit register containing the data for pins p9 7 to p9 0 . when the cpu reads p9dr, for output pins it reads the value in the p9dr latch, but for input pins, it obtains the pin status directly. 9.10.3 pin functions the pin functions of port 9 are the same in all mcu operating modes. as figure 9-21 indicated, these pins are used for output of on-chip timer signals and for input and output of serial data and clock signals as well as for general-purpose input and output. specifically, they carry output signals for free-running timers 2 and 3, pulse-width modulation (pwm) timer output signals, and input and output signals for the serial communication interfaces. bit 7 6 5 4 3 2 1 0 p9 7 ddr p9 6 ddr p9 5 ddr p9 4 ddr p9 3 ddr p9 2 ddr p9 1 ddr p9 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit 7 6 5 4 3 2 1 0 p9 7 p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 179
table 9-17 shows how the functions of the pins of port 9 are selected. table 9-17 port 9 pin functions pin selection of pin functions p9 7 / the function depends on the communication mode bit (c/a) in the sci1 serial mode sck 1 register (smr) and the clock enable 1 and 0 bits (cke1 and cke0) in the sci1 serial control register (scr). c/a 0 1 cke1 0 1 0 1 cke0 0 1 0 1 0 1 0 1 pin function p9 7 sci1 sci1 external sci1 internal sci1 external input/ internal clock input clock output clock input output clock output when used for p9 7 input/output, the input or output function is selected by p9 7 ddr. p9 6 / rxd 1 the function depends on the receive enable bit (re) in the sci1 serial control register (scr) and on the p9 6 ddr bit as follows. re 0 1 p9 6 ddr 0 1 0 1 pin function p9 6 input p9 6 output rxd 1 input p9 5 / txd 1 the function depends on the transmit enable bit (te) in sci1s scr and on the p9 6 ddr bit as follows. te 0 1 p9 5 ddr 0 1 0 1 pin function p9 5 input p9 5 output txd 1 output 180
table 9-17 port 9 pin functions (cont) pin selection of pin functions p9 4 / sck 2 / the function depends on the output enable bit (oe) of pwm timer 3s timer control pw 3 register (tcr), the c/a bit in sci2s smr, the cke1 and cke0 bits in sci2s scr, and the port 9 pwm enable bit (p9pwme) and port 9 serial enable bit (p9sci2e) in system control register 2 (syscr2). p9sci2e 1 0 1 0 p9pwme 0 1 1 0 oe 0/1 0 1 0/1 c/a 0 1 0/1 0/1 0/1 cke1 0 1 0 1 0/1 0/1 0/1 cke0 0 1 0 1 0 1 0 1 0/1 0/1 0/1 pin function p9 4 sci2 sci2 sci2 sci2 p9 4 pw 3 p9 4 input/ internal external internal external input/ output input/ output clock clock clock clock output output output input output input when used for p9 4 input/output, the input or output function is selected by p9 4 ddr. p9 3 / rxd 2 / the function depends on the oe bit in pwm timer 2s tcr, the re bit in sci2s pw 2 scr, and the p9pwme bit and p9sci2e bit in syscr2. p9sci2e 1 0 0 1 p9pwme 0 1 0 1 oe 0 1 0 1 0 1 0/1 0/1 re 0 1 0 1 0 1 0/1 0/1 pin function p9 3 rxd 2 p9 3 pw 2 p9 3 input/ input input/ output input/ output output output when used for p9 3 input/output, the input or output function is selected by p9 3 ddr. 181
table 9-17 port 9 pin functions (cont) pin selection of pin functions p9 2 / txd 2 / the function depends on the oe bit in pwm timer 1s tcr, the te bit in sci2s pw 1 scr, and the p9pwme bit and p9sci2e bit in syscr2. p9sci2e 1 0 0 1 p9pwme 0 1 0 1 oe 0 1 0 1 0 1 0/1 0/1 te 0 1 0 1 0 1 0/1 0/1 pin function p9 2 txd 2 p9 2 pw 1 p9 2 input/ output input/ output input/ output output output when used for p9 2 input/output, the input or output function is selected by p9 2 ddr. p9 1 / the function depends on the output enable a bit (oea) in frt3s tcr and on the ftoa 3 p9 1 ddr bit as follows. oea 0 1 p9 1 ddr 0 1 0 1 pin function p9 1 input p9 1 output ftoa 3 output p9 0 / the function depends on the output enable a bit (oea) in frt2s tcr and on the ftoa 2 p9 0 ddr bit as follows. oea 0 1 p9 0 ddr 0 1 0 1 pin function p9 0 input p9 0 output ftoa 2 output 182
section 10 16-bit free-running timers 10.1 overview the h8/534 and h8/536 have an on-chip 16-bit free-running timer (frt) module with three independent channels (frt1, frt2, and frt3). all three channels are functionally identical. each channel has a 16-bit free-running counter that it uses as a time base. applications of the frt module include rectangular-wave output (up to two independent waveforms per channel), input pulse width measurement, and measurement of external clock periods. 10.1.1 features the features of the free-running timer module are listed below. selection of four clock sources the free-running counters can be driven by an internal clock source (?4, ?8, or ?32), or an external clock input (enabling use as an external event counter). two independent comparators each free-running timer channel can generate two independent waveforms. input capture function the current count can be captured on the rising or falling edge (selectable) of an input signal. four types of interrupts compare-match a and b, input capture, and overflow interrupts can be requested independently. the compare-match and input capture interrupts can be served by the data transfer controller (dtc), enabling interrupt-driven data transfer with minimal cpu programming. counter can be cleared under program control the free-running counters can be cleared on compare-match a. 183
10.1.2 block diagram figure 10-1 shows a block diagram of one free-running timer channel. ici ocia ocib fovi interrupt signals ocra: ocrb: frc: icr: tcsr: tcr: output compare register a output compare register b free running counter input capture register timer control/status register timer control register tcr tcsr icr ocrb comparator b capture compare-match b clear overflow frc comparator a ocra control logic ftoa ftob fti ftci external clock internal clock ?4 ?8 ?32 clock clock select compare-match a module data bus internal data bus bus interface figure 10-1 block diagram of 16-bit free-running timer 184
10.1.3 input and output pins table 10-1 lists the input and output pins of the free-running timer module. table 10-1 input and output pins of free-running timer module channel name abbreviation i/o function 1 output compare a ftoa 1 output output controlled by comparator a of fr t1 output compare b or ftob 1 / output / output controlled by comparator b of fr t1, counter clock input ftci 1 input or input of external clock source for frt1 input capture fti 1 input t rigger for capturing current count of fr t1 2 output compare a ftoa 2 output output controlled by comparator a of fr t2 output compare b or ftob 2 / output / output controlled by comparator b of fr t2, counter clock input ftci 2 input or input of external clock source for frt2 input capture fti 2 input t rigger for capturing current count of fr t2 3 output compare a ftoa 3 output output controlled by comparator a of fr t3 output compare b or ftob 3 / output / output controlled by comparator b of fr t3, counter clock input ftci 3 input or input of external clock source for frt3 input capture fti 3 input t rigger for capturing current count of fr t3 185
10.1.4 register configuration table 10-2 lists the registers of each free-running timer channel. table 10-2 register configuration initial channel name abbreviation r/w value address timer control register tcr r/w h'00 h'fe90 timer control/status register tcsr r/(w) * h'00 h'fe91 free-running counter (high) frc (h) r/w h'00 h'fe92 free-running counter (low) frc (l) r/w h'00 h'fe93 1 output compare register a (high) ocra (h) r/w h'ff h'fe94 output compare register a (low) ocra (l) r/w h'ff h'fe95 output compare register b (high) ocrb (h) r/w h'ff h'fe96 output compare register b (low) ocrb (l) r/w h'ff h'fe97 input capture register (high) icr (h) r h'00 h'fe98 input capture register (low) icr (l) r h'00 h'fe99 timer control register tcr r/w h'00 h'fea0 timer control/status register tcsr r/(w) * h'00 h'fea1 free-running counter (high) frc (h) r/w h'00 h'fea2 free-running counter (low) frc (l) r/w h'00 h'fea3 2 output compare register a (high) ocra (h) r/w h'ff h'fea4 output compare register a (low) ocra (l) r/w h'ff h'fea5 output compare register b (high) ocrb (h) r/w h'ff h'fea6 output compare register b (low) ocrb (l) r/w h'ff h'fea7 input capture register (high) icr (h) r h'00 h'fea8 input capture register (low) icr (l) r h'00 h'fea9 * software can write a 0 to clear bits 7 to 4, but cannot write a 1 in these bits. 186
table 10-2 register configuration (cont) initial channel name abbreviation r/w value address timer control register tcr r/w h'00 h'feb0 timer control/status register tcsr r/(w) * h'00 h'feb1 free-running counter (high) frc (h) r/w h'00 h'feb2 free-running counter (low) frc (l) r/w h'00 h'feb3 3 output compare register a (high) ocra (h) r/w h'ff h'feb4 output compare register a (low) ocra (l) r/w h'ff h'feb5 output compare register b (high) ocrb (h) r/w h'ff h'feb6 output compare register b (low) ocrb (l) r/w h'ff h'feb7 input capture register (high) icr (h) r h'00 h'feb8 input capture register (low) icr (l) r h'00 h'feb9 * software can write a 0 to clear bits 7 to 4, but cannot write a 1 in these bits. 10.2 register descriptions 10.2.1 free-running counter (frc)?'fe92, h'fea2, h'feb2 each frc is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a clock source. the clock source is selected by the clock select 1 and 0 bits (cks1 and cks0) of the timer control register (tcr). the frc can be cleared by compare-match a. when the frc overflows from h'ffff to h'0000, the overflow flag (ovf) in the timer control/status register (tcsr) is set to 1. because the frc is a 16-bit register, a temporary register (temp) is used when the frc is written or read. see section 10.3, ?pu interface?for details. the frcs are initialized to h'0000 at a reset and in the standby modes. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 read/writer/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 187
10.2.2 output compare registers a and b (ocra and ocrb)?'fe94 and h'fe96, h'fea4 and h'fea6, h'feb4 and h'feb6 ocra and ocrb are 16-bit readable/writable registers, the contents of which are continually compared with the value in the frc. when a match is detected, the corresponding output compare flag (ocfa or ocfb) is set in the timer control/status register (tcsr). in addition, if the output enable bit (oea or oeb) in the timer control register (tcr) is set to 1, when the output compare register and frc values match, the logic level selected by the output level bit (olvla or olvlb) in the timer control status register (tcsr) is output at the output compare pin (ftoa or ftob). the ftoa and ftob output are 0 before the first compare-match. because ocra and ocrb are 16-bit registers, a temporary register (temp) is used when they are written. see section 10.3, ?pu interface?for details. ocra and ocrb are initialized to h'ffff at a reset and in the standby modes. 10.2.3 input capture register (icr)?'fe98, h'fea8, h'feb8 the icr is a 16-bit read-only register. when the rising or falling edge of the signal at the input capture input pin is detected, the current value of the frc is copied to the icr. at the same time, the input capture flag (icf) in the timer control/status register (tcsr) is set to 1. the input capture edge is selected by the input edge select bit (iedg) in the tcsr. because the icr is a 16-bit register, a temporary register (temp) is used when the icr is written or read. see section 10.3, ?pu interface?for details. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 read/writer/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 read/write r r r r r r r r r r r r r r r r 188
to ensure input capture, the pulse width of the input capture signal should be at least 1.5 system clock periods (1.5). the icr is initialized to h'0000 at a reset and in the standby modes. note: when input capture is detected, the frc value is transferred to the icr even if the input capture flag (icf) is already set. 10.2.4 timer control register (tcr) the tcr is an 8-bit readable/writable register that selects the frc clock source, enables the output compare signals, and enables interrupts. the tcr is initialized to h'00 at a reset and in the standby modes. bit 7?nput capture interrupt enable (icie): this bit selects whether to request an input capture interrupt (ici) when the input capture flag (icf) in the timer status/control register (tcsr) is set to 1. bit 7 icie description 0 the input capture interrupt request (ici) is disabled. (initial value) 1 the input capture interrupt request (ici) is enabled. bit 6?utput compare interrupt enable b (ocieb): this bit selects whether to request output compare interrupt b (ocib) when output compare flag b (ocfb) in the timer status/control register (tcsr) is set to 1. fti minimum fti pulse width bit 7 6 5 4 3 2 1 0 icie ocieb ociea ovie oeb oea cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 189
bit 6 ocieb description 0 output compare interrupt request b (ocib) is disabled. (initial value) 1 output compare interrupt request b (ocib) is enabled. bit 5?utput compare interrupt enable a (ociea): this bit selects whether to request output compare interrupt a (ocia) when output compare flag a (ocfa) in the timer status/control register (tcsr) is set to 1. bit 5 ociea description 0 output compare interrupt request a (ocia) is disabled. (initial value) 1 output compare interrupt request a (ocia) is enabled. bit 4?imer overflow interrupt enable (ovie): this bit selects whether to request a free- running timer overflow interrupt (fovi) when the timer overflow flag (ovf) in the timer status/control register (tcsr) is set to 1. bit 4 ovie description 0 the free-running timer overflow interrupt request (fovi) is disabled. (initial value) 1 the free-running timer overflow interrupt request (fovi) is enabled. bit 3?utput enable b (oeb): this bit selects whether to enable or disable output of the logic level selected by the olvlb bit in the timer status/control register (tcsr) at the output compare b pin when the frc and ocrb values match. bit 3 oeb description 0 output compare b output is disabled. (initial value) 1 output compare b output is enabled. bit 2?utput enable a (oea): this bit selects whether to enable or disable output of the logic level selected by the olvla bit in the timer status/control register (tcsr) at the output compare a pin when the frc and ocra values match. 190
bit 2 oea description 0 output compare a output is disabled. (initial value) 1 output compare a output is enabled. bits 1 and 0?lock select (cks1 and cks0): these bits select external clock input or one of three internal clock sources for the frc. external clock pulses are counted on the rising edge. bit 1 bit 0 cks1 cks0 description 0 0 internal clock source (?4) (initial value) 0 1 internal clock source (?8) 1 0 internal clock source (?32) 1 1 external clock source (counted on the rising edge) 10.2.5 timer control/status register (tcsr) the tcsr is an 8-bit readable and partially writable* register that selects the input capture edge and output compare levels, and specifies whether to clear the counter on compare-match a. it also contains four status flags. the tcsr is initialized to h'00 at a reset and in the standby modes. * software can write a 0 in bits 7 to 4 to clear the flags, but cannot write a 1 in these bits. bit 7?nput capture flag (icf): this status flag is set to 1 to indicate an input capture event. it signifies that the frc value has been copied to the icr. bit 7 6 5 4 3 2 1 0 icf ocfb ocfa ovf olvlb olvla iedg cclra initial value 0 0 0 0 0 0 0 0 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/w r/w r/w r/w 191
bit 7 icf description 0 this bit is cleared from 1 to 0 when: (initial value) 1. the cpu reads the icf bit after it has been set to 1, then writes a 0 in this bit. 2. the data transfer controller (dtc) serves an input capture interrupt . 1 this bit is set to 1 when an input capture signal causes the frc value to be copied to the icr. bit 6?utput compare flag b (ocfb): this status flag is set to 1 when the frc value matches the ocrb value. bit 6 ocfb description 0 this bit is cleared from 1 to 0 when: (initial value) 1. the cpu reads the ocfb bit after it has been set to 1, then writes a 0 in this bit. 2. the data transfer controller (dtc) serves output compare interrupt b. 1 this bit is set to 1 when frc = ocrb. bit 5?utput compare flag a (ocfa): this status flag is set to 1 when the frc value matches the ocra value. bit 5 ocfa description 0 this bit is cleared from 1 to 0 when: (initial value) 1. the cpu reads the ocfa bit after it has been set to 1, then writes a 0 in this bit. 2. the data transfer controller (dtc) serves output compare interrupt a. 1 this bit is set to 1 when frc = ocra. bit 4?imer overflow flag (ovf): this status flag is set to 1 when the frc overflows (changes from h'ffff to h'0000). bit 4 ovf description 0 this bit is cleared from 1 to 0 when the cpu reads (initial value) the ovf bit after it has been set to 1, then writes a 0 in this bit. 1 this bit is set to 1 when frc changes from h'ffff to h'0000. bit 3?utput level b (olvlb): this bit selects the logic level to be output at the ftob pin when the frc and ocrb values match. 192
bit 3 olvlb description 0 a 0 logic level (low) is output for compare-match b. (initial value) 1 a 1 logic level (high) is output for compare-match b. bit 2?utput level a (olvla): this bit selects the logic level to be output at the ftoa pin when the frc and ocra values match. bit 2 olvla description 0 a 0 logic level (low) is output for compare-match a. (initial value) 1 a 1 logic level (high) is output for compare-match a. bit 1?nput edge select (iedg): this bit selects whether to capture the count on the rising or falling edge of the input capture signal. bit 1 iedg description 0 the frc value is copied to the icr on the falling edge (initial value) of the input capture signal. 1 the frc value is copied to the icr on the rising edge of the input capture signal. bit 0?ounter clear a (cclra): this bit selects whether to clear the frc at compare-match a (when the frc and ocra values match). bit 0 cclra description 0 the frc is not cleared. (initial value) 1 the frc is cleared at compare-match a. 193
10.3 cpu interface the frc, ocra, ocrb, and icr are 16-bit registers, but they are connected to an 8-bit data bus. when the cpu accesses these four registers, to ensure that both bytes are written or read simultaneously, the access is performed using an 8-bit temporary register (temp). these registers are written and read as follows. register write when the cpu writes to the upper byte, the upper byte of write data is placed in temp. next, when the cpu writes to the lower byte, this byte of data is combined with the byte in temp and all 16 bits are written in the register simultaneously. register read when the cpu reads the upper byte, the upper byte of data is sent to the cpu and the lower byte is placed in temp. when the cpu reads the lower byte, it receives the value in temp. programs that access these four registers should normally use word access. equivalently, they may access first the upper byte, then the lower byte. data will not be transferred correctly if the bytes are accessed in reverse order, or if only one byte is accessed. coding examples : write the contents of r0 into ocra in frt1 mov.w r0, @h'fe94 : read icr of frt2 mov.w, @h'fea8, r0 the same considerations apply to access by the dtc. figure 10-2 shows the data flow when the frc is accessed. the other registers are accessed in the same way, except that when ocra or ocrb is read, the upper and lower bytes are both transferred directly to the cpu without using the temporary register. 194
< lower byte write > cpu writes data h'55 bus interface temp [h'aa] frch [h'aa] frcl [h'55] module data bus fig. 10-2 (a) < upper byte write > cpu writes data h'aa bus interface temp [h'aa] frch [ ] frcl [ ] module data bus figure 10-2 (a) write access to frc (when cpu writes h'aa55) 195
10.4 operation 10.4.1 frc incrementation timing the frc increments on a pulse generated once for each period of the selected (internal or external) clock source. if external clock input is selected, the frc increments on the rising edge of the clock signal. figure 10-3 shows the increment timing. < lower byte read > cpu writes data h'55 bus interface temp [h'55] module data bus fig. 10-2 (b) < upper byte read > cpu writes data h'aa bus interface temp [h'55] module data bus frch [ ] frcl [ ] frch [h'aa] frcl [h'55] figure 10-2 (b) read access to frc (when frc contains h'aa55) 196
the pulse width of the external clock signal must be at least 1.5 clock periods. the counter will not increment correctly if the pulse width is shorter than 1.5 clock periods. 10.4.2 output compare timing setting of output compare flags a and b (ocfa and ocfb): the output compare flags are set to 1 by an internal compare-match signal generated when the frc value matches the ocra or ocrb value. this compare-match signal is generated at the last state in which the two values match, just before the frc increments to a new value. accordingly, when the frc and ocr values match, the compare-match signal is not generated until the next period of the clock source. figure 10-4 shows the timing of the setting of the output compare flags. ftci minimum ftci pulse width fig. 10-3 external clock source frc clock pulse frc n n + 1 figure 10-3 increment timing for external clock input 197
output timing: when a compare-match occurs, the logic level selected by the output level bit (olvla or olvlb) in the tcsr is output at the output compare pin (ftoa or ftob). figure 10-5 shows the timing of this operation for compare-match a. frc ocr n n n + 1 internal compare- match signal ocf fig. 10-5 ftoa internal compare- match a signal olyla figure 10-4 setting of output compare flags figure 10-5 timing of output compare a 198
frc clear timing: if the cclra bit is set to 1, the frc is cleared when compare-match a occurs. figure 10-6 shows the timing of this operation. 10.4.3 input capture timing 1. input capture timing: an internal input capture signal is generated from the rising or falling edge of the input at the input capture pin (fti), as selected by the iedg bit in the tcsr. figure 10-7 shows the usual input capture timing when the rising edge is selected (iedg = 1). but if the upper byte of the icr is being read when the input capture signal arrives, the internal input capture signal is delayed by one state. figure 10-8 shows the timing for this case. internal compare- match a signal frc n h'0000 input at fti pin internal input capture signal figure 10-6 clearing of frc by compare-match a figure 10-7 input capture timing (usual case) 199
timing of input capture flag (icf) setting: the input capture flag (icf) is set to 1 by the internal input capture signal. figure 10-9 shows the timing of this operation. read cycle: cpu reads upper byte of icr t 1 t 2 t 3 input at fti pin internal input capture signal internal input capture signal icr icf frc n n ?1 n n + 1 figure 10-8 input capture timing (1-state delay) figure 10-9 setting of input capture flag 200
10.4.4 setting of frc overflow flag (ovf) the frc overflow flag (ovf) is set to 1 when the frc overflows (changes from h'ffff to h'0000). figure 10-10 shows the timing of this operation. 10.5 cpu interrupts and dtc interrupts each free-running timer channel can request four types of interrupts: input capture (ici), output compare a and b (ocia and ocib), and overflow (fovi). each interrupt is requested when the corresponding enable and flag bits are set. independent signals are sent to the interrupt controller for each type of interrupt. table 10-3 lists information about these interrupts. table 10-3 free-running timer interrupts interrupt description dtc service available? priority ici requested when icf is set yes high ocia requested when ocfa is set yes ocib requested when ocfb is set yes fovi requested when ovf is set no low the ici, ocia, and ocib interrupts can be directed to the data transfer controller (dtc) to have a data transfer performed in place of the usual interrupt-handling routine. when the dtc serves one of these interrupts, it automatically clears the icf, ocfa, or ocfb flag to 0. see section 6, ?ata transfer controller?for further information on the dtc. internal overflow signal ovf frc h'ffff h'0000 figure 10-10 setting of overflow flag (ovf) 201
10.6 synchronization of free-running timers 1 to 3 10.6.1 synchronization after a reset the three free-running timer channels are synchronized at a reset and remained synchronized until: the clock source is changed; frc contents are rewritten; or an frc is cleared. after a reset, each free-running counter operates on the ?4 internal clock source. 10.6.2 synchronization by writing to frcs when synchronization among free-running timers 1 to 3 is lost, it can be restored by writing to the free-running counters. synchronization on internal clock source: when an internal clock is selected, free-running timers 1 to 3 can be synchronized by writing data to their free-running counters as indicated in table 10-4. table 10-4 synchronization by writing to frcs clock source write interval write data ?4 4n (states) m (frc1) ?8 8n (states) m + n (frc2) ?32 32n (states) m + 2n (frc3) m, n: arbitrary integers after writing these data, synchronization can be checked by reading the three free-running counters at the same interval as the write interval. if the read data have the same relative differences as the write data, the three free-running timers are synchronized. programs for synchronizing the timers are shown next. examples a, b, and c can be used when the program is stored in on-chip memory. examples d, e, and f can be used when the program is stored in external memory. these programs assume that no wait states (t w ) are inserted and there is no nmi input. 202
example a: ?4 clock source, 12-state write interval (n = 3), on-chip memory la: ldc.b #h'fe,br ; initialize base register for short-format instruction (mov:s) ldc.w #h'0700,sr ; raise interrupt mask level to 7 mov.w #m,r1 ; data for free-running timer 1 mov.w #m+3,r2 ; data for free-running timer 2 (m + n = m + 3) mov.w #m+6,r3 ; data for free-running timer 3 (m + 2n = m + 2 3) bsr set4 ; call write routine .align 2 ; align write instructions (mov:s) at even address set4:mov:s.w r1,@h'92:8 ; write to frc 1 (address h'fe92) 9 states brn set4:8 ; 2-byte dummy instruction 3 states mov:s.w r2,@h'a2:8 ; write to frc 2 (address h'fea2) total 12 states brn set4:8 ; 2-byte dummy instruction mov:s.w r3,@h'b2:8 ; write to frc 3 (address h'feb2) rts example b: ?8 clock source, 16-state write interval (n = 2), on-chip memory lb: ldc.b #h'fe,br ldc.w #h'0700,sr mov.w #m,r1 mov.w #m+2,r2 mov.w #m+4,r3 bsr set8 .align 2 set8:mov:s.w r1,@h'92:8 ; 9 states brn set8:8 ; 3 states total 16 states xch r1,r1 ; 4 states mov:s.w r2,@h'a2:8 brn set8:8 xch r2,r2 mov:s.w r3,@h'b2:8 rts 203
example c: ?32 clock source, 32-state write interval (n = 1), on-chip memory lc: ldc.b #h'fe,br ldc.w #h'0700,sr mov.w #m,r1 mov.w #m+1,r2 mov.w #m+2,r3 bsr set32 .align 2 ; align on even address set32: mov:s.w r1,@h'92:8 ; 2 bytes, 9 states bsr wait:8 ; 2 bytes, 9 states mov:s.w r2,@h'a2:8 bsr wait:8 total 32 states mov:s.w r3,@h'b2:8 rts .align 2 ; align on even address wait: nop ; 2 states xch r1,r1 ; 4 states rts ; 8 states note: the stack is assumed to be in on-chip ram. example d: ?4 clock source, 20-state write interval (n = 5), external memory ld: ldc.b #h'fe,br ldc.w #h'0700,sr ; set interrupt mask level to 7 clr.b h'ff10 ; disable wait states mov.w #m,r1 mov.w #m+5,r2 mov.w #m+10,r3 mov:s.w r1,@h'92:8 ; 13 states brn ld:8 ; 2 bytes, 7 states mov:s.w r2,@h'a2:8 brn ld:8 mov:s.w r3,@h'b2:8 total 20 states 204
example e: ?8 clock source, 24-state write interval (n = 3), external memory le: ldc.b #h'ff,br ldc.w #h'0700,sr clr.b @h'f8"8 mov.w #m,r1 mov.w #m+3,r2 mov.w #m+6,r3 mov:s.w r1,@h'92:8 ; 13 states brn le:8 ; 2 bytes, 7 states total 24 states nop ; 1 byte, 4 states mov:s.w r2,@h'a2:8 brn le:8 nop mov:s.w r3,@h'b2:8 example f: ?32 clock source, 32-state write interval (n = 1), external memory lf: ldc.b #h'ff,br ldc.w #h'0700,sr clr.b @h'f8:8 mov.w #m,r1 mov.w #m+1,r2 mov.w #m+2,r3 mov:s.w r1,@h'92:8 ; external memory, so 13 states xch r0,r0 ; 8 states brn lf:8 ; 2 bytes, 7 states nop ; 4 states mov:s.w r2,@h'a2:8 xch r0,r0 brn lf:8 nop mov:s.w r3,@h'b2:8 total 32 states 205
synchronization on external clock source: when the external clock source is selected, the free-running timers can be synchronized by halting their external clock inputs, then writing identical values in their free-running counters. 10.7 sample application in the example below, one free-running timer channel is used to generate two square-wave outputs with a 50% duty factor and arbitrary phase relationship. the programming is as follows: 1. the cclra bit in the tcsr is set to 1. 2. each time a compare-match interrupt occurs, software inverts the corresponding output level bit in the tcsr. 10.8 application notes application programmers should note that the following types of contention can occur in the free- running timers. contention between frc write and clear: if an internal counter clear signal is generated during the t 3 state of a write cycle to the lower byte of a free-running counter, the clear signal takes priority and the write is not performed. frc h'ffff ocra ocrb h'0000 ftoa pin ftob pin clear counter figure 10-11 square-wave output (example) 206
figure 10-12 shows this type of contention. contention between frc write and increment: if an frc increment pulse is generated during the t 3 state of a write cycle to the lower byte of a free-running counter, the write takes priority and the frc is not incremented. write cycle: cpu writes to lower byte of frc t 1 t 2 t 3 internal address bus internal write signal frc clear signal frc n h'0000 frc address figure 10-12 frc write-clear contention 207
figure 10-13 shows this type of contention. write cycle: cpu writes to lower byte of frc t 1 t 2 t 3 internal address bus internal write signal frc clock pulse frc n m frc address write data figure 10-13 frc write-increment contention 208
contention between ocr write and compare-match: if a compare-match occurs during the t 3 state of a write cycle to the lower byte of ocra or ocrb, the write takes precedence and the compare-match signal is inhibited. figure 10-14 shows this type of contention. incrementation caused by changing of internal clock source: when an internal clock source is changed, the changeover may cause the frc to increment. this depends on the time at which the clock select bits (cks1 and cks0) are rewritten, as shown in table 10-5. the pulse that increments the frc is generated at the falling edge of the internal clock source. if clock sources are changed when the old source is high and the new source is low, as in case no. 3 in table 10-5, the changeover generates a falling edge that triggers the frc increment pulse. switching between an internal and external clock source can also cause the frc to increment. write cycle: cpu writes to lower byte of ocra or ocrb t 1 t 2 t 3 ocr address n n n + 1 m write data inhibited compare-match a or b signal ocra or ocrb frc internal write signal internal address bus figure 10-14 contention between ocr write and compare-match 209
table 10-5 effect of changing internal clock sources no. description timing chart 1 low ? low: cks1 and cks0 are rewritten while both clock sources are low. 2 low ? high: cks1 and cks0 are rewritten while old clock source is low and new clock source is high. 3 high ? low: cks1 and cks0 are rewritten while old clock source is high and new clock source is low. * the switching of clock sources is regarded as a falling edge that increments the frc. cks rewrite old clock source new clock source frc clock pulse frc n n + 1 cks rewrite old clock source new clock source frc clock pulse frc n n + 1 n + 2 cks rewrite old clock source new clock source frc clock pulse frc n n + 1 n + 2 * 210
table 10-5 effect of changing internal clock sources (cont) no. description timing chart 4 high ? high: cks1 and cks0 are rewritten while both clock sources are high. cks rewrite old clock source new clock source frc clock pulse frc n n + 1 n + 2 211
section 11 8-bit timer 11.1 overview the h8/534 and h8/536 have a single 8-bit timer based on an 8-bit counter (tcnt). the timer has two time constant registers (tcora and tcorb) that are constantly compared with the tcnt value to detect compare-match events. one application of the 8-bit timer is to generate a rectangular-wave output with an arbitrary duty factor. 11.1.1 features the features of the 8-bit timer are listed below. selection of four clock sources the counter can be driven by an internal clock signal (?8, ?64, or ?1024) or an external clock input (enabling use as an external event counter). selection of three ways to clear the counter the counter can be cleared on compare-match a or b, or by an external reset signal. timer output controlled by two time constants the single timer output (tmo) is controlled by two independent time constants, enabling the timer to generate output waveforms with an arbitrary duty factor. three types of interrupts compare-match a and b and overflow interrupts can be requested independently. the compare match interrupts can be served by the data transfer controller (dtc), enabling interrupt-driven data transfer with minimal cpu programming. 213
11.1.2 block diagram figure 11-1 shows a block diagram of 8-bit timer. compare-match b clear overflow clock compare-match a internal clocks external clocks tmci tmo tmri clock select ?8 ?64 ?1024 control logic tcora comparator a tcnt comparator b tcorb tcsr tcr cmia cmib ovi interrupt signals bus interface module data bus internal data bus tcora: tcorb: tcnt: tcsr: tcr: time constant register a time constant register b timer counter timer control/status register timer control register figure 11-1 block diagram of 8-bit timer 214
11.1.3 input and output pins table 11-1 lists the input and output pins of the 8-bit timer. table 11-1 input and output pins of 8-bit timer name abbreviation i/o function timer output tmo output output controlled by compare-match timer clock input tmci input external clock source for the counter timer reset input tmri input external reset signal for the counter 11.1.4 register configuration table 11-2 lists the registers of the 8-bit timer. table 11-2 8-bit timer registers name abbreviation r/w initial value address timer control register tcr r/w h'00 h'fed0 timer control/status register tcsr r/(w) * h'10 h'fed1 timer constant register a tcora r/w h'ff h'fed2 timer constant register b tcorb r/w h'ff h'fed3 timer counter tcnt r/w h'00 h'fed4 * software can write a 0 to clear bits 7 to 5, but cannot write a 1 in these bits. 11.2 register descriptions 11.2.1 timer counter (tcnt)?'fed4 the timer counter (tcnt) is an 8-bit up-counter that increments on a pulse generated from one of four clock sources. the clock source is selected by clock select bits 2 to 0 (cks2 to cks0) of the timer control register (tcr). the cpu can always read or write the timer counter. bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 215
the timer counter can be cleared by an external reset input or by an internal compare-match signal generated at a compare-match event. clock clear bits 1 and 0 (cclr1 and cclr0) of the timer control register select the method of clearing. when the timer counter overflows from h'ff to h'00, the overflow flag (ovf) in the timer control/status register (tcsr) is set to 1. the timer counter is initialized to h'00 at a reset and in the standby modes. 11.2.2 time constant registers a and b (tcora and tcorb)?'fed2 and h'fed3 tcora and tcorb are 8-bit readable/writable registers. the timer count is continually compared with the constants written in these registers. when a match is detected, the corresponding compare-match flag (cmfa or cmfb) is set in the timer control/status register (tcsr). the timer output signal (tmo) is controlled by these compare-match signals as specified by output select bits 1 to 0 (os1 to os0) in the timer status/control register (tcsr). tcora and tcorb are initialized to h'ff at a reset and in the standby modes. 11.2.3 timer control register (tcr)?'fed0 the tcr is an 8-bit readable/writable register that selects the clock source and the time at which the timer counter is cleared, and enables interrupts. the tcr is initialized to h'00 at a reset and in the standby modes. bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 216
bit 7?ompare-match interrupt enable b (cmieb): this bit selects whether to request compare-match interrupt b (cmib) when compare-match flag b (cmfb) in the timer status/control register (tcsr) is set to 1. bit 7 cmieb description 0 compare-match interrupt request b (cmib) is disabled. (initial value) 1 compare-match interrupt request b (cmib) is enabled. bit 6?ompare-match interrupt enable a (cmiea): this bit selects whether to request compare-match interrupt a (cmia) when compare-match flag a (cmfa) in the timer status/control register (tcsr) is set to 1. bit 6 cmiea description 0 compare-match interrupt request a (cmia) is disabled. (initial value) 1 compare-match interrupt request a (cmia) is enabled. bit 5?imer overflow interrupt enable (ovie): this bit selects whether to request a timer overflow interrupt (ovi) when the overflow flag (ovf) in the timer status/control register (tcsr) is set to 1. bit 5 ovie description 0 the timer overflow interrupt request (ovi) is disabled. (initial value) 1 the timer overflow interrupt request (ovi) is enabled. bits 4 and 3?ounter clear 1 and 0 (cclr1 and cclr0): these bits select how the timer counter is cleared: by compare-match a or b or by an external reset input. bit 4 bit 3 cclr1 cclr0 description 0 0 not cleared. (initial value) 0 1 cleared on compare-match a. 1 0 cleared on compare-match b. 1 1 cleared on rising edge of external reset input signal. 217
bits 2, 1, and 0?lock select (cks2, cks1, and cks0): these bits select the internal or external clock source for the timer counter. for the external clock source they select whether to increment the count on the rising or falling edge of the clock input, or on both edges. bit 2 bit 1 bit 0 cks2 cks1 cks0 description 0 0 0 no clock source (timer stopped). (initial value) 0 0 1 internal clock source (?8). 0 1 0 internal clock source (?64). 0 1 1 internal clock source (?1024). 1 0 0 no clock source (timer stopped). 1 0 1 external clock source, counted on the rising edge. 1 1 0 external clock source, counted on the falling edge. 1 1 1 external clock source, counted on both the rising and falling edges. 11.2.4 timer control/status register (tcsr)?'fed1 the tcsr is an 8-bit readable and partially writable* register that indicates compare-match and overflow status and selects the effect of compare-match events on the timer output signal (tmo). the tcsr is initialized to h'10 at a reset and in the standby modes. * software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits. bit 7?ompare-match flag b (cmfb): this status flag is set to 1 when the timer count matches the time constant set in tcorb. bit 7 6 5 4 3 2 1 0 cmfb cmfa ovf os3 os2 os1 os0 initial value 0 0 0 1 0 0 0 0 read/write r/(w) * r/(w) * r/(w) * r/w r/w r/w r/w 218
bit 7 cmfb description 0 this bit is cleared from 1 to 0 when: (initial value) 1. the cpu reads the cmfb bit after it has been set to 1, then writes a 0 in this bit. 2. compare-match interrupt b is served by the data transfer controller (dtc). 1 this bit is set to 1 when tcnt = tcorb. bit 6?ompare-match flag a (cmfa): this status flag is set to 1 when the timer count matches the time constant set in tcora. bit 6 cmfa description 0 this bit is cleared from 1 to 0 when: (initial value) 1. the cpu reads the cmfa bit after it has been set to 1, then writes a 0 in this bit. 2. compare-match interrupt a is served by the data transfer controller (dtc). 1 this bit is set to 1 when tcnt = tcora. bit 5?imer overflow flag (ovf): this status flag is set to 1 when the timer count overflows (changes from h'ff to h'00). bit 5 ovf description 0 this bit is cleared from 1 to 0 when the cpu reads (initial value) the ovf bit after it has been set to 1, then writes a 0 in this bit. 1 this bit is set to 1 when tcnt changes from h'ff to h'00. bit 4?eserved: this bit cannot be modified and is always read as 1. bits 3 to 0?utput select 3 to 0 (os3 to os0): these bits specify the ef fect of compare-match events on the timer output signal (tmo). bits os3 and os2 control the ef fect of compare-match b on the output level. bits os1 and os0 control the ef fect of compare-match a on the output level. when all four output select bits are cleared to 0 the tmo signal is not output. the tmo output is 0 before the first compare-match. bit 3 bit 2 os3 os2 description 0 0 no change when compare-match b occurs. (initial value) 0 1 output changes to 0 when compare-match b occurs. 1 0 output changes to 1 when compare-match b occurs. 1 1 output inverts (toggles) when compare-match b occurs. 219
bit 1 bit 0 os1 os0 description 0 0 no change when compare-match a occurs. (initial value) 0 1 output changes to 0 when compare-match a occurs. 1 0 output changes to 1 when compare-match a occurs. 1 1 output inverts (toggles) when compare-match a occurs. 11.3 operation 11.3.1 tcnt incrementation timing the timer counter increments on a pulse generated once for each period of the selected (internal or external) clock source. if external clock input (tmci) is selected, the timer counter can increment on the rising edge, the falling edge, or both edges of the external clock signal. the external clock pulse width must be at least 1.5 clock periods for incrementation on a single edge, and at least 2.5 clock periods for incrementation on both edges. the counter will not increment correctly if the pulse width is shorter than these values. tmci minimum tmci pulse width (single-edge incrementation) tmci minimum tmci pulse width (double-edge incrementation) 220
figure 11-2 shows the count timing for incrementation on both edges. 11.3.2 compare match timing setting of compare-match flags a and b (cmfa and cmfb): the compare-match flags are set to 1 by an internal compare-match signal generated when the timer count matches the time constant in tcora or tcorb. the compare-match signal is generated at the last state in which the match is true, just before the timer counter increments to a new value. accordingly, when the timer count matches one of the time constants, the compare-match signal is not generated until the next period of the clock source. figure 11-3 shows the timing of the setting of the compare-match flags. n ?1 n tcnt tcnt clock pulse external clock source n + 1 figure 11-2 count timing for external clock input 221
output timing: when a compare-match event occurs, the timer output (tmo) changes as specified by the output select bits (os3 to os0) in the tcsr. depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. figure 11-4 shows the timing when the output is set to toggle on compare-match a. n internal compare-match signal tcor tcnt n + 1 cmf n internal compare-match a signal timer output (tmo) figure 11-3 setting of compare-match flags figure 11-4 timing of timer output 222
timing of compare-match clear: depending on the cclr1 and cclr0 bits in the tcr, the timer counter can be cleared when compare-match a or b occurs. figure 11-5 shows the timing of this operation. 11.3.3 external reset of tcnt when the cclr1 and cclr0 bits in the tcr are both set to 1, the timer counter is cleared on the rising edge of an external reset input. figure 11-6 shows the timing of this operation. n h'00 internal compare-match signal tcnt h'00 n ?1 n tcnt internal clear pulse external reset input (tmri) figure 11-5 timing of compare-match clear figure 11-6 timing of external reset 223
11.3.4 setting of tcnt overflow flag the overflow flag (ovf) is set to 1 when the timer count overflows (changes from h'ff to h'00). figure 11-7 shows the timing of this operation. 11.4 cpu interrupts and dtc interrupts the 8-bit timer can generate three types of interrupts: compare-match a and b (cmia and cmib), and overflow (ovi). each interrupt is requested when the corresponding enable and flag bits are set in the tcr and tcsr. independent signals are sent to the interrupt controller for each type of interrupt. table 11-3 lists information about these interrupts. table 11-3 8-bit timer interrupts interrupt description dtc service available? priority cmia requested when cmfa is set yes high cmib requested when cmfb is set yes ovi requested when ovf is set no low the cmia and cmib interrupts can be served by the data transfer controller (dtc) to have a data transfer performed. when the dtc serves one of these interrupts, it automatically clears the cmfa or cmfb flag to 0. see section 6, ?ata transfer controller?for further information on the dtc. h'ff internal overflow signal tcnt h'00 ovf figure 11-7 setting of overflow flag (ovf) 224
11.5 sample application in the example below, the 8-bit timer is used to generate a pulse output with a selected duty factor. the control bits are set as follows: 1. in the tcr, cclr1 is cleared to 0 and cclr0 is set to 1 so that the timer counter is cleared when its value matches the constant in tcora. 2. in the tcsr, bits os3 to os0 are set to ?110,?causing the output to change to 1 on compare- match a and to 0 on compare-match b. with these settings, the 8-bit timer provides output of pulses at a rate determined by tcora with a pulse width determined by tcorb. no software intervention is required. tcnt h'ff tcora tcorb h'00 tmo pin clear counter figure 11-8 example of pulse output 225
11.6 application notes application programmers should note that the following types of contention can occur in the 8-bit timer. contention between tcnt write and clear: if an internal counter clear signal is generated during the t 3 state of a write cycle to the timer counter, the clear signal takes priority and the write is not performed. figure 11-9 shows this type of contention. tcnt address n h'00 internal address bus internal write signal counter clear signal tcnt write cycle: cpu writes to tcnt t 1 t 2 t 3 figure 11-9 tcnt write-clear contention 226
contention between tcnt write and increment: if a timer counter increment pulse is generated during the t 3 state of a write cycle to the timer counter, the write takes priority and the timer counter is not incremented. figure 11-10 shows this type of contention. tcnt address n m write data internal address bus internal write signal tcnt clock pulse tcnt write cycle: cpu writes to tcnt t 1 t 2 t 3 figure 11-10 tcnt write-increment contention 227
contention between tcor write and compare-match: if a compare-match occurs during the t 3 state of a write cycle to tcora or tcorb, the write takes precedence and the compare- match signal is inhibited. figure 11-11 shows this type of contention. contention between compare-match a and compare-match b: if identical time constants are written in tcora and tcorb, causing compare-match a and b to occur simultaneously, any conflict between the output selections for compare-match a and b is resolved by following the priority order in table 11-4. tcnt address n n + 1 n m write cycle: cpu writes to tcora or tcorb t 1 t 2 t 3 tcor write data inhibited internal address bus internal write signal tcnt tcora or tcorb compare-match a or b signal figure 11-11 contention between tcor write and compare-match 228
table 11-4 priority order of timer output output selection priority toggle high 1 output 0 output no change low incrementation caused by changing of internal clock source: when an internal clock source is changed, the changeover may cause the timer counter to increment. this depends on the time at which the clock select bits (cks2 to cks0) are rewritten, as shown in table 11-5. the pulse that increments the timer counter is generated at the falling edge of the internal clock source signal. if clock sources are changed when the old source is high and the new source is low, as in case no. 3 in table 11-5, the changeover generates a falling edge that triggers the tcnt clock pulse and increments the timer counter. switching between an internal and external clock source can also cause the timer counter to increment. table 11-5 effect of changing internal clock sources no. description timing chart 1 low ? low * 1 : cks1 and cks0 are rewritten while both clock sources are low. note: * 1 including a transition from low to the stopped state (cks1 = 0, cks0 = 0), or a transition from the stopped state to low. cks rewrite old clock source tcnt clock pulse new clock source tcnt n n + 1 229
table 11-5 effect of changing internal clock sources (cont) no. description timing chart 2 low ? high * 1 : cks1 and cks0 are rewritten while old clock source is low and new clock source is high. 3 high ? low * 2 : cks1 and cks0 are rewritten while old clock source is high and new clock source is low. note: * 1 including a transition from the stopped state to high. * 2 including a transition from high to the stopped state. * 3 the switching of clock sources is regarded as a falling edge that increments the tcnt. cks rewrite old clock source new clock source tcnt clock pulse tcnt n n + 1 n + 2 cks rewrite old clock source new clock source tcnt clock pulse tcnt n n + 1 n + 2 * 3 230
table 11-5 effect of changing internal clock sources (cont) no. description timing chart 4 high ? high: cks1 and cks0 are rewritten while both clock sources are high. cks rewrite old clock source new clock source tcnt clock pulse tcnt n n + 1 n + 2 231
section 12 pwm timer 12.1 overview the h8/534 and h8/536 have an on-chip pulse-width modulation (pwm) timer module with three independent channels (pwm1, pwm2, and pwm3). all three channels are functionally identical. using an 8-bit timer counter, each pwm channel generates a rectangular output pulse with a duty factor of 0 to 100%. the duty factor is specified in an 8-bit duty register (dtr). 12.1.1 features the pwm timer module has the following features: selection of eight clock sources duty factors from 0 to 100% with 1/250 resolution output with positive or negative logic 12.1.2 block diagram figure 12-1 shows a block diagram of one pwm timer channel. 233
12.1.3 input and output pins table 12-1 lists the output pins of the pwm timer module. there are no input pins. table 12-1 output pins of pwm timer module name abbreviation i/o function pwm1 output pw 1 output pulse output from pwm timer channel 1. pwm2 output pw 2 output pulse output from pwm timer channel 2. pwm3 output pw 3 output pulse output from pwm timer channel 3. dtr: tcnt: tcr: duty register timer counter timer control register clock clock select internal clock source ?2 ?8 ?32 ?128 ?256 ?1024 ?2048 ?4096 bus interface internal data bus module data bus tcr pw dtr tcnt comparator output control compare- match figure 12-1 block diagram of pwm timer 234
12.1.4 register configuration the pwm timer module has three registers for each channel as listed in table12-2. table 12-2 pwm timer registers initial channel name abbreviation r/w value address 1 timer control register tcr r/w h'38 h'fec0 duty register dtr r/w h'ff h'fec1 timer counter tcnt r/(w) * h'00 h'fec2 2 timer control register tcr r/w h'38 h'fec4 duty register dtr r/w h'ff h'fec5 timer counter tcnt r/(w) * h'00 h'fec6 3 timer control register tcr r/w h'38 h'fec8 duty register dtr r/w h'ff h'fec9 timer counter tcnt r/(w) * h'00 h'feca * the timer counters are read/write registers, but the write function is for test purposes only. application programs should never write to these registers. 12.2 register descriptions 12.2.1 timer counter (tcnt)?'fec2, h'fec4, h'feca the pwm timer counters (tcnt) are 8-bit up-counters. when the output enable bit (oe) in the timer control register (tcr) is set to 1, the timer counter starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (cks2 to cks0). after counting from h'00 to h'f9, the timer counter repeats from h'00. the pwm timer counters can be read and written, but the write function is for test purposes only. application software should never write to a pw timer counter, because this may have unpredictable effects. bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 235
the pwm timer counters are initialized to h'00 at a reset and in the standby modes, and when the oe bit is cleared to 0. 12.2.2 duty register (dtr)?'fec1, h'fec5, h'fec9 the duty registers (dtr) specify the duty factor of the output pulse. any duty factor from 0 to 100% can be selected, with a resolution of 1/250. writing 0 (h'00) in a dtr gives a 0% duty factor; writing 125 (h'7d) gives a 50% duty factor; writing 250 (h'fa) gives a 100% duty factor. the timer count is continually compared with the dtr contents. if the dtr value is not 0, when the count increments from h'00 to h'01 the pwm output signal is set to 1. when the count increments to the dtr value, the pwm output returns to 0. if the dtr value is 0 (duty factor 0%), the pwm output remains constant at 0. the dtrs are double-buffered. a new value written in a dtr while the timer counter is running does not become valid until after the count changes from h'f9 to h'00. when the timer counter is stopped (while the oe bit is 0), new values become valid as soon as written. when a dtr is read, the value read is the currently valid value. the dtrs are initialized to h'ff at a reset and in the standby modes. 12.2.3 timer control register (tcr)?'fec0, h'fec4, h'fec8 the tcrs are 8-bit readable/writable registers that select the clock source and control the pwm outputs. the tcrs are initialized to h'38 at a reset and in the standby modes. bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 oe os cks2 cks1 cks0 initial value 0 0 1 1 1 0 0 0 read/write r/w r/w r/w r/w r/w 236
bit 7?utput enable (oe): this bit enables the timer counter and the pwm output. bit 7 oe description 0 pwm output is disabled. tcnt is cleared to h'00 and stopped. (initial value) 1 pwm output is enabled. tcnt runs. bit 6?utput select (os): this bit selects positive or negative logic for the pwm output. bit 6 os description 0 positive logic; positive-going pwm pulse, 1 = high (initial value) 1 negative logic; negative-going pwm pulse, 1 = low bits 5 to 3?eserved: these bits cannot be modified and are always read as 1. bits 2, 1, and 0?lock select (cks2, cks1, and cks0): these bits select one of eight clock sources obtained by dividing the system clock (?. bit 2 bit 1 bit 0 cks2 cks1 cks0 description 0 0 0 ?2 (initial value) 0 0 1 ?8 0 1 0 ?32 0 1 1 ?128 1 0 0 ?256 1 0 1 ?1024 1 1 0 ?2048 1 1 1 ?4096 from the clock source frequency, the resolution, period, and frequency of the pwm output can be calculated as follows. resolution = 1/clock source frequency pwm period = resolution 250 pwm frequency = 1/pwm period if the ?clock frequency is 10 mhz, then the resolution, period, and frequency of the pwm output for each clock source are given in table12-3. 237
table 12-3 pwm timer parameters for 10 mhz system clock internal clock frequency resolution pwm period pwm frequency ?2 200 ns 50 s 20 khz ?8 800 ns 200 s 5 khz ?32 3.2 s 800 s 1.25 khz ?128 12.8 s 3.2 ms 312.5 hz ?256 25.6 s 6.4 ms 156.3 hz ?1024 102.4 s 25.6 ms 39.1 hz ?2048 204.8 s 51.2 ms 19.5 hz ?4096 409.6 s 102.4 ms 9.8 hz 12.3 operation figure 12-2 shows the timing of the pwm timer operation. 1. positive logic (os = 0) (1) when oe = 0?a) in figure 12-2: the timer count is held at h'00 and pwm output is inhibited. (the pin is used for port 9 input/output, and its state depends on the corresponding port 9 data register and data direction register.) any value (such as n in figure 12-2) written in the dtr becomes valid immediately. (2) when oe = 1 i) the timer counter begins incrementing, and the pwm output goes high. [(b) in figure 12-2] ii) when the count reaches the dtr value, the pwm output goes low. [(c) in figure 12-2] iii)if the dtr value is changed (by writing the data m in figure 12-2), the new value becomes valid after the timer count changes from h'f9 to h'00. [(d) in figure 12-2] 2. negative logic (os = 1): the operation is the same except that high and low are reversed in the pwm output. [(e) in figure 12-2] 238
fig. 12-2 tcnt clock pulses oe tcnt (os = ?? dtr pwm output (os = ?? * h'ff (d) m n written in dtr * (b) (a) (e) (a) h'00 m written in dtr (b) h'01 h'02 n ?1 n + 1 n n h'f9 (c) (c) (d) h'00 h'01 * used for port 9 input/output: state depends on values in data register and data direction register. figure 12-2 pwm timing 239
12.4 application notes notes on the use of the pwm timer module are given below. to use port 9 for pwm output, first set the p9pwme bit to 1 and clear the p9sci2e bit to 0 in system control register 2 (syscr2). similarly, to use port 6 for pwm output, first set the p6pwme bit to 1 and clear the corresponding interrupt enable bit or bits (irq 3 e, irq 4 e, irq 5 e) to 0 in syscr2. 1. any necessary changes to the clock select bits (cks2 to cks0) and output select bit (os) should be made before the output enable bit (oe) is set to 1. 2. if the dtr value is h'00, the duty factor is 0% and pw output remains constant at 0. if the dtr value is h'fa to h'ff, the duty factor is 100% and pw output remains constant at 1. (for positive logic, 0 is low and 1 is high. for negative logic, 0 is high and 1 is low.) 3. pwm output and serial communication interface functions cannot be mixed among pins p9 4 , p9 3 , and p9 2 . 240
section 13 watchdog timer 13.1 overview the h8/534 and h8/536 have an on-chip watchdog timer (wdt) module. this module can monitor system operation by generating a signal that resets the entire chip if a system crash allows the timer count to overflow. when this watchdog function is not needed, the wdt module can be used as an interval timer. in the interval timer mode, an interval timer interrupt is requested at each counter overflow. the wdt module is also used in recovering from the software standby mode. 13.1.1 features the basic features of the watchdog timer module are summarized as follows: selection of eight clock sources selection of two modes: watchdog timer mode and interval timer mode counter overflow generates a reset signal or interrupt request reset signal in watchdog timer mode; interval timer interrupt request in interval timer mode. external output of reset signal the reset signal generated in watchdog timer mode resets the entire h8/534 or h8/536 chip. depending on a reset output enable bit, the reset signal can also be output from the res pin to reset devices controlled by the h8/534 or h8/536. 241
13.1.2 block diagram figure 13-1 is a block diagram of the watchdog timer. 13.1.3 register configuration table 13-1 lists information on the watchdog timer registers. table 13-1 register configuration initial addresses name abbreviation r/w value write read timer control/status register tcsr r/(w) * h'18 h'feec h'feec timer counter tcnt r/w h'00 h'feec h'feed reset control/status register rstcsr r/(w) * h'3f h'ff14 h'ff15 * software can write a 0 to clear the status flag bits, but cannot write 1. interrupt control read/ write control tcnt tcsr rstcsr reset control clock select ?2 ?32 ?64 ?128 ?256 ?512 ?2048 ?4096 interval timer mode internal clock sources interrupt signal reset (internal, external) tcnt tcsr rstcsr : timer counter : timer control/status register : reset control/status register clock internal data bus overflow figure 13-1 block diagram of timer counter 242
13.2 register descriptions 13.2.1 timer counter tcnt?'feec (write), h'feed (read) the watchdog timer counter (tcnt) is a readable/writable* 8-bit up-counter. when the timer enable bit (tme) in the timer control/status register (tcsr) is set to 1, the timer counter starts counting pulses of an internal clock source selected by clock select bits 2 to 0 (cks2 to cks0) in the tcsr. when the count overflows (changes from h'ff to h'00), an overflow flag (ovf) in the tcsr is set to 1. the watchdog timer counter is initialized to h'00 at a reset and when the tme bit is cleared to 0. * tcnt is write-protected by a password. see section 13.2.4, ?otes on register access?for details. 13.2.2 timer control/status register (tcsr)?'feec the watchdog timer control/status register (tcsr) is an 8-bit readable/writable *2 register that selects the timer mode and clock source and performs other functions. bits 7 to 5 are initialized to 0 at a reset and in the standby modes. bits 2 to 0 are initialized to 0 at a reset, but retain their values in the standby modes. *1 software can write a 0 in bit 7 to clear the flag, but cannot set this bit to 1. *2 the tcsr is write-protected by a password. see section 13.2.4, ?otes on register access for details. bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 ovf wt/it tme cks2 cks1 cks0 initial value 0 0 0 1 1 0 0 0 read/write r/(w) * 1 r/w r/w r/w r/w r/w 243
bit 7?verflow flag (ovf): this bit indicates that the watchdog timer count has overflowed. bit 7 ovf description 0 this bit is cleared to from 1 to 0 when the cpu reads (initial value) the ovf bit after it has been set to 1, then writes a 0 in this bit. 1 this bit is set to 1 when tcnt changes from h'ff to h'00. * * ovf is not set in watchdog timer mode. bit 6?imer mode select (wt/it): this bit selects whether to operate in the watchdog timer mode or interval timer mode. bit 6 wt/it description 0 interval timer mode (interval timer interrupt request) (initial value) 1 watchdog timer mode (reset) bit 5?imer enable (tme): this bit enables or disables the timer. bit 5 tme description 0 tcnt is initialized to h'00 and stopped. (initial value) 1 tcnt runs. a reset or interrupt request is generated when the count overflows. bits 4 and 3?eserved: these bits cannot be modified and are always read as 1. bits 2, 1, and 0?lock select (cks2, cks1, and cks0): these bits select one of eight clock sources obtained by dividing the system clock (?. the overflow interval listed in the table below is the time from when the watchdog timer counter begins counting from h'00 until an overflow occurs. 244
bit 2 bit 1 bit 0 description cks2 cks1 cks0 clock source overflow interval (?= 10 mhz) 0 0 0 ?2 51.2s (initial value) 0 0 1 ?32 819.2s 0 1 0 ?64 1.6ms 0 1 1 ?128 3.3ms 1 0 0 ?256 6.6ms 1 0 1 ?512 13.1ms 1 1 0 ?2048 52.4ms 1 1 1 ?4096 104.9ms 13.2.3 reset control/status register (rstcsr)?'ff14 (write), h'ff15 (read) the reset control/status register (rstcsr) is an 8-bit readable/writable *2 register that indicates when a reset has been caused by a watchdog timer overflow, and controls external output of the reset signal. bit 6 is not initialized by the reset caused by the watchdog timer overflow. it is initialized, however, by a reset caused by input at the res pin. *1 software can write a 0 in bit 7 to clear the flag, but cannot set this bit to 1. *2 the rstcsr is write-protected by a password. see section 13.2.4, ?otes on register access?for details. bit 7?atchdog timer reset (wrst): this bit indicates that a reset signal has been generated by a watchdog timer overflow in the watchdog timer mode. the reset signal generated by the overflow resets the entire h8/534 or h8/536 chip. in addition, if the reset output enable (rstoe) bit is set to 1, the reset signal (low) is output at the res pin to reset devices connected to the h8/534 or h8/536. the wrst bit can be cleared by software by writing a 0. it is also cleared when a reset signal from an external device is received at the res pin. bit 7 6 5 4 3 2 1 0 wrst rstoe initial value 0 0 1 1 1 1 1 1 read/write r/(w) * 1 r/w 245
bit 7 wrst description 0 this bit is cleared to 0 by a reset signal input from the res pin, (initial state) or when the cpu reads wrst after it has been set to 1, then writes a 0 in this bit. 1 this bit is set to 1 when the watchdog timer overflows in the watchdog timer mode and an internal reset signal is generated. bit 6?eset output enable (rstoe): this bit selects whether the reset signal generated by a watchdog timer overflow in the watchdog timer mode is output from the res pin. bit 6 rstoe description 0 the reset signal generated by watchdog timer overflow is not (initial state) output to external devices. 1 the reset signal generated by watchdog timer overflow is output to external devices. bits 5 to 0?eserved: these bits cannot be modified and are always read as 1. 13.2.4 notes on register access the watchdog timers tcnt, tcsr, and rstcsr registers differ from other registers in being more difficult to write. the procedures for writing and reading these registers are given below. writing to tcnt and tcsr: these registers must be written by word access. programs cannot write to them by byte access. the word must contain the write data and a password. the watchdog timers tcnt and tcsr registers both have the same write address. the write data must be contained in the lower byte of the word written at this address. the upper byte must contain h'5a (password for tcnt) or h'a5 (password for tcsr). see figure 13-2. the result of the access depicted in figure 13-2 is to transfer the write data from the lower byte to the tcnt or tcsr. 246
writing to rstcsr: the rstcsr must be written by moving word data to address h'ff14. it cannot be written by byte access. the upper byte of the word must contain a password. separate passwords are used for clearing the wrst bit and for writing a 1 or 0 to the rstoe bit. to clear the wrst bit, the word written at address h'ff14 must contain the password h'a5 in the upper byte and the data h'00 in the lower byte. this clears the wrst bit to 0. to set or clear the rstoe bit, the word written at address h'ff14 must contain the password h'5a in the upper byte and the write data in the lower byte. the value of bit 6 in the lower byte is written in the rstoe bit. these write operations are illustrated in figure 13-3. write to tcnt 15 8 7 0 address h'ffec h'5a write data write to tcsr 15 8 7 0 address h'ffec h'a5 write data to write 0 to the wrst bit 15 8 7 0 address h'ff14 h'a5 h'00 to write to the rstoe bit 15 8 7 0 address h'ff14 h'5a write data figure 13-2 writing to tcnt and tcsr figure 13-3 writing to rstcsr 247
reading tcnt, tcsr, and rstcsr: the read addresses are h'feec for tcsr, h'feed for tcnt, and h'ff15 for rstcsr as indicated in table 13-2. these three registers are read like other registers. byte access instructions can be used. table 13-2 read addresses of tcnt and tcsr read address register h'ffec tcsr h'ffed tcnt h'ff15 rstcsr 13.3 operation 13.3.1 watchdog timer mode the watchdog timer function begins operating when software sets the wt/it and tme bits to 1 in the tcsr. thereafter, software should periodically rewrite the contents of the timer counter (normally by writing h'00) to prevent the count from overflowing. if a program crash allows the timer count to overflow, the watchdog timer generates a reset as shown in figure 13-4. the reset signal from the watchdog timer can also be output from the res pin to reset external devices. this reset output signal is a low pulse with a duration of 132 ?clock periods. the reset signal is output only if the rstoe bit in the rstcsr is set to 1. the reset generated by the watchdog timer has the same vector as a reset generated by low input at the res pin. software should check the wrst bit in the rstcsr to determine the source of the reset. if a watchdog timer overflow occurs at the same time as a low input at the res pin, priority is given to one type of reset or the other depending on the value of the rstoe bit in the rstcsr. if the rstoe bit is set to 1 when both types of reset occur simultaneously, the watchdog timers reset signal takes precedence. the internal state of the h8/534 or h8/536 chip is reset and the res pin is held low for 132 ?clock periods. if at the end of 520 ?clock periods there is still an external low input to the res pin, the external reset takes effect, clearing the wrst and rstoe bits to 0. note that if the external reset occurs before the watchdog timer overflows, it takes effect immediately and clears the rstoe bit. if the rstoe bit is cleared to 0 when both types of reset occur simultaneously, the reset signal input from the res pin takes precedence and the wrst bit is cleared to 0. 248
13.3.2 interval timer mode interval timer operation begins when the wt/it bit is cleared to 0 and the tme bit is set to 1. in the interval timer mode, an interval timer interrupt request is generated each time the timer count overflows. this function can be used to generate interrupts at regular intervals. see figure 13-5. h'ff tcnt count h'00 watchdog timer overflow start h'00 written to tcnt ovf = 1 reset start h'00 written to tcnt internal reset signal external reset signal (res) * * the reset signals are output for 132 ?clock periods. the internal reset signal remains valid for 520 ?clock periods. figure 13-4 operation in watchdog timer mode h'ff tcnt count h'00 wt/it = 0 tme = 1 * time t * * * * * interval timer interrupt request figure 13-5 operation in interval timer mode 249
13.3.3 operation in software standby mode the watchdog timer has a special function in recovery from software standby mode. specific watchdog timer settings are required when the software standby mode is used. before transition to the software standby mode: the tme bit must be cleared to 0 to stop the watchdog timer counter before a transition to the software standby mode. the chip cannot enter the software standby mode while the tme bit is set to 1. before entering the software standby mode, software should also set the clock select bits (cks2 to cks0) to a value that makes the timer overflow interval equal to or greater than the stabilization time of the clock oscillator. recovery from the software standby mode: recovery from the software standby mode can be triggered by an nmi request. in this case the recovery proceeds as follows: when an nmi request signal is received, the clock oscillator starts running and the watchdog timer starts counting at the rate selected by the clock select bits before the software standby mode was entered. when the count overflows from h'ff to h'00, the ?clock is presumed to be stable and usable, clock signals are supplied to all modules on the chip, the standby mode ends, and the nmi interrupt-handling routine starts executing. 13.3.4 setting of overflow flag the ovf bit is set to 1 when the timer count overflows in the interval timer mode. simultaneously, the wdt module requests an interval timer interrupt. the timing is shown in figure 13-6. tcnt internal overflow signal ovf h'ff h'00 figure 13-6 setting of ovf bit 250
13.3.5 setting of watchdog timer reset (wrst) bit the wrst bit is valid when wt/it = 1 and tme = 1. the wrst bit is set to 1 when the timer count overflows. an internal reset signal is simultaneously generated for the entire h8/534 or 536 chip. the timing is shown in figure 13-7. tcnt overflow signal wrst h'ff h'00 internal reset signal figure 13-7 setting of wrst bit and internal reset signal 251
13.4 application notes contention between tcnt write and increment: if a timer counter clock pulse is generated during the t 3 state of a write cycle to the timer counter, the write operation takes priority and the timer counter is not incremented. see figure 13-8. changing the clock select bits (cks2 to cks0): software should stop the watchdog timer (by clearing the tme bit to 0) before changing the value of the clock select bits. if the clock select bits are modified while the watchdog timer is running, the timer count may be incremented incorrectly. use of reset output: when the reset signal is output to external devices, special circuitry is needed for input of the external reset signal. the reset output is an nmos open-drain output. figure 13-9 shows an example of a reset circuit. internal address bus internal write signal tcnt clock pulse tcnt address n m write cycle: cpu writes to tcnt tcnt counter write data t 1 t 2 t 3 figure 13-8 tcnt write-increment contention 252
h8/534 h8/536 4.7 k res reset switch w 60 pf * 74ls05 external reset signal 2sc2618 or equivalent 1.0 ? 74hc14 maximum value of wiring capacitance * 100 k w 1.0 k w figure 13-9 reset circuit (example) 253
section 14 serial communication interface 14.1 overview the h8/534 and h8/536 have two serial communication interface channels (sci1 and sci2) for transferring serial data to and from other chips. each channel supports both synchronous and asynchronous data transfer. communication control functions are provided by eight internal registers. 14.1.1 features the features of the on-chip serial communication interface are: selection of asynchronous or synchronous mode ?asynchronous mode sci1 and sci2 can communicate with a uart (universal asynchronous receiver/transmitter), acia (asynchronous communication interface adapter), or other chip that employs standard asynchronous serial communication. eight data formats are available. ?data length: 7 or 8 bits ?stop bit length: 1 or 2 bits ?parity: even, odd, or none ?error detection: parity, overrun, and framing errors ?synchronous mode sci1 and sci2 can communicate with chips able to synchronize data transfers with clock pulses. ?data length: 8 bits ?error detection: overrun errors full duplex communication the transmitting and receiving sections are independent, so each channel can transmit and receive simultaneously. both the transmit and receive sections use double buffering, so continuous data transfer is possible in either direction. built-in baud rate generator any specified bit rate can be generated. internal or external clock source the baud rate generator can operate on an internal clock source, or an external clock signal input at the sck pin. three interrupts transmit-end, receive-end, and receive-error interrupts are requested independently. the transmit-end and receive-end interrupts can be served by the on-chip data transfer controller (dtc), providing a convenient way to transfer data with minimal cpu programming. 255
14.1.2 block diagram figure 14-1 shows a block diagram of one serial communication interface channel. rxd txd sck rdr: rsr: tdr: tsr: ssr: scr: smr: brr: receive data register receive shift register transmit data register transmit shift register serial status register serial control register serial mode register bit rate register rdr ssr tdr scr smr brr baud-rate generator tsr rsr communication control parity generator parity check clock external clock module data bus internal data bus internal clock source txi rxi eri interrupt signals ?4 ?16 ?64 bus interface figure 14-1 block diagram of serial communication interface 256
14.1.3 input and output pins table 14-1 lists the input and output pins used by the sci module. table 14-1 sci input/output pins channel name abbreviation i/o function 1 serial clock sck 1 input/output serial clock input and output. receive data rxd 1 input receive data input. transmit data txd 1 output transmit data output. 2 serial clock sck 2 input/output serial clock input and output. receive data rxd 2 input receive data input. transmit data txd 2 output transmit data output. 14.1.4 register configuration table 14-2 lists the sci registers. table 14-2 sci registers channel name abbreviation r/w initial value address 1 receive shift register rsr receive data register rdr r h'00 h'fedd transmit shift register tsr transmit data register tdr r/w h'ff h'fedb serial mode register smr r/w h'04 h'fed8 serial control register scr r/w h'0c h'feda serial status register ssr r/(w) * h'87 h'fedc bit rate register brr r/w h'ff h'fed9 2 receive shift register rsr receive data register rdr r h'00 h'fef5 transmit shift register tsr transmit data register tdr r/w h'ff h'fef3 serial mode register smr r/w h'04 h'fef0 serial control register scr r/w h'0c h'fef2 serial status register ssr r/(w) * h'87 h'fef4 bit rate register brr r/w h'ff h'fef1 * software can write a 0 to clear the status flag bits, but cannot write a 1. 257
14.2 register descriptions 14.2.1 receive shift register (rsr) the rsr receives incoming data bits. when one data character has been received, it is transferred to the receive data register (rdr). the cpu cannot read or write the rsr directly. 14.2.2 receive data register (rdr)?'fedd, h'fef5 the rdr stores received data. as each character is received, it is transferred from the rsr to the rdr, enabling the rsr to receive the next character. this double-buffering allows the sci to receive data continuously. the cpu can read but not write the rdr. the rdr is initialized to h'00 at a reset and in the standby modes. 14.2.3 transmit shift register (tsr) the tsr holds the character currently being transmitted. when transmission of this character is completed, the next character is moved from the transmit data register (tdr) to the tsr and transmission of that character begins. if the tdr does not contain valid data, the sci stops transmitting. the cpu cannot read or write the tsr directly. bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r bit 7 6 5 4 3 2 1 0 read/write bit 7 6 5 4 3 2 1 0 read/write 258
14.2.4 transmit data register (tdr)?'fedb, h'fef3 the tdr is an 8-bit readable/writable register that holds the next character to be transmitted. when the tsr becomes empty, the character written in the tdr is transferred to the tsr. continuous data transmission is possible by writing the next byte in the tdr while the current byte is being transmitted from the tsr. the tdr is initialized to h'ff at a reset and in the standby modes. 14.2.5 serial mode register (smr)?'fed8, h'fef0 the smr is an 8-bit readable/writable register that controls the communication format and selects the clock rate for the internal clock source. it is initialized to h'04 at a reset and in the standby modes. bit 7?ommunication mode (c/a): this bit selects the asynchronous or synchronous communication mode. bit 7 c/a description 0 asynchronous communication. (initial value) 1 communication is synchronized with the serial clock. bit 6?haracter length (chr): this bit selects the character length in asynchronous mode. it is ignored in synchronous mode. bit 6 chr description 0 8 bits per character. (initial value) 1 7 bits per character. bit 7 6 5 4 3 2 1 0 c/a chr pe o/e stop cks1 cks0 initial value 0 0 0 0 0 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w 259
bit 5?arity enable (pe): this bit selects whether to add a parity bit in asynchronous mode. it is ignored in synchronous mode. bit 5 pe description 0 transmit: no parity bit is added. (initial value) receive: parity is not checked. 1 transmit: a parity bit is added. receive: parity is not checked. bit 4?arity mode (o/e): in asynchronous mode, when parity is enabled (pe = 1), this bit selects even or odd parity. even parity means that a parity bit is added to the data bits for each character to make the total number of 1s even. odd parity means that the total number of 1s is made odd. this bit is ignored when pe = 0 and in the synchronous mode. bit 4 o/e description 0 even parity. (initial value) 1 odd parity. bit 3?top bit length (stop): this bit selects the number of stop bits. it is ignored in the synchronous mode. bit 3 stop description 0 1 stop bit. (initial value) 1 2 stop bits. bit 2?eserved: this bit cannot be modified and is always read as 1. bits 1 and 0?lock select 1 and 0 (cks1 and cks0): these bits select the internal clock source when the baud rate generator is clocked from within the h8/534 or h8/536 chip. bit 1 bit 0 cks1 cks0 description 0 0 ?clock (initial value) 0 1 ?4 clock 1 0 ?16 clock 1 1 ?64 clock 260
14.2.6 serial control register (scr)?'feda, h'fef2 the scr is an 8-bit readable/writable register that enables or disables various sci functions. it is initialized to h'0c at a reset and in the standby modes. bit 7?ransmit interrupt enable (tie): this bit enables or disables the transmit-end interrupt (txi) requested when the transmit data register empty (tdre) bit in the serial status register (ssr) is set to 1. bit 7 tie description 0 the transmit-end interrupt request (txi) is disabled. (initial value) 1 the transmit-end interrupt request (txi) is enabled. bit 6?eceive interrupt enable (rie): this bit enables or disables the receive-end interrupt (rxi) requested when the receive data register full (rdrf) bit in the serial status register (ssr) is set to 1. it also enables and disables the receive-error interrupt (eri) request. bit 6 rie description 0 the receive-end interrupt (rxi) and receive-error interrupt (eri) (initial value) requests are disabled. 1 the receive-end interrupt (rxi) and receive-error interrupt (eri) requests are enabled. bit 5?ransmit enable (te): this bit enables or disables the transmit function. when the transmit function is enabled, the txd pin is automatically used for output. when the transmit function is disabled, the txd pin can be used as a general-purpose i/o port. bit 5 te description 0 the transmit function is disabled. the txd pin can be (initial value) used as a general-purpose i/o port. 1 the transmit function is enabled. the txd pin is used for output. bit 7 6 5 4 3 2 1 0 tie rie te re cke1 cke0 initial value 0 0 0 0 1 1 0 0 read/write r/w r/w r/w r/w r/w r/w 261
bit 4?eceive enable (re): this bit enables or disables the receive function. when the receive function is enabled, the rxd pin is automatically used for input. when the receive function is disabled, the rxd pin is available as a general-purpose i/o port. bit 4 re description 0 the receive function is disabled. the rxd pin can be (initial value) used as a general-purpose i/o port. 1 the receive function is enabled. the rxd pin is used for input. bits 3 and 2?eserved: these bits cannot be modified and are always read as 1. bit 1?lock enable 1 (cke1): this bit selects the internal or external clock source for the baud rate generator. when the external clock source is selected, the sck pin is automatically used for input of the external clock signal. bit 1 cke1 description 0 internal clock source. (initial value) 1 external clock source. (the sck pin is used for input.) bit 0?lock enable 0 (cke0): when an internal clock source is used in synchronous mode, this bit enables or disables serial clock output at the sck pin. this bit is ignored when the external clock is selected, or when the asynchronous mode is selected. for further information on the communication format and clock source selection, see tables 14-5 and 14-6 in section 14.3, ?peration. bit 0 cke0 description 0 the sck pin is not used by the sci (and is available as (initial value) a general-purpose i/o port). 1 the sck pin is used for serial clock output. 262
14.2.7 serial status register (ssr)?'fedc, h'fef4 * software can write a 0 to clear the flags, but cannot write a 1 in these bits. the ssr is an 8-bit register that indicates transmit and receive status. it is initialized to h'87 at a reset and in the standby modes. bit 7?ransmit data register empty (tdre): this bit indicates when the tdr contents have been transferred to the tsr and the next character can safely be written in the tdr. bit 7 tdre description 0 this bit is cleared from 1 to 0 when: 1. the cpu reads the tdre bit after it has been set to 1, then writes a 0 in this bit. 2. the data transfer controller (dtc) writes data in the tdr. 1 this bit is set to 1 at the following times: (initial value) 1. the chip is reset or enters a standby mode. 2. when tdr contents are transferred to the tsr. 3. when tdre = 0 and the te bit is cleared to 0. bit 6?eceive data register full (rdrf): this bit indicates when one character has been received and transferred to the rdr. bit 6 rdrf description 0 this bit is cleared from 1 to 0 when: (initial value) 1. the cpu reads the rdrf bit after it has been set to 1, then writes a 0 in this bit. 2. the data transfer controller (dtc) reads the rdr. 3. the chip is reset or enters a standby mode. 1 this bit is set to 1 when one character is received without error and transferred from the rsr to the rdr. bit 7 6 5 4 3 2 1 0 tdre rdrf orer fer per initial value 1 0 0 0 0 1 1 1 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * 263
bit 5?verrun error (orer): this bit indicates an overrun error during reception. bit 5 orer description 0 this bit is cleared from 1 to 0 when: (initial value) 1. the cpu reads the orer bit after it has been set to 1, then writes a 0 in this bit. 2. the chip is reset or enters a standby mode. 1 this bit is set to 1 if reception of the next character ends while the receive data register is still full (rdrf = 1). bit 4?raming error (fer): this bit indicates a framing error during data reception in the synchronous mode. it has no meaning in the asynchronous mode. bit 4 fer description 0 this bit is cleared to from 1 to 0 when: (initial value) 1. the cpu reads the fer bit after it has been set to 1, then writes a 0 in this bit. 2. the chip is reset or enters a standby mode. 1 this bit is set to 1 if a framing error occurs (stop bit = 0). bit 3?arity error (per): this bit indicates a parity error during data reception in the asynchronous mode, when a communication format with parity bits is used. this bit has no meaning in the synchronous mode, or when a communication format without parity bits is used. bit 3 per description 0 this bit is cleared from 1 to 0 when: (initial value) 1. the cpu reads the per bit after it has been set to 1, then writes a 0 in this bit. 2. the chip is reset or enters a standby mode. 1 this bit is set to 1 when a parity error occurs (the parity of the received data does not match the parity selected by the bit in the smr). bits 2 to 0?eserved: these bits cannot be modified and are always read as 1. 264
14.2.8 bit rate register (brr)?'fed9, h'fef1 the brr is an 8-bit register that, together with the cks1 and cks0 bits in the smr, determines the bit rate output by the baud rate generator. the brr is initialized to h'ff (the slowest rate) at a reset and in the standby modes. tables 14-3 and 14-4 show examples of brr (n) and cks (n) settings for commonly used bit rates. table 14-3 examples of brr settings in asynchronous mode (1) xtal frequency (mhz) 2 2.4576 4 4.194304 bit error error error error rate n n (%) n n (%) n n (%) n n (%) 110 1 70 +0.03 1 86 +0.31 1 141 +0.03 1 148 ?.04 150 0 207 +0.16 0 255 0 1 103 +0.16 1 108 +0.21 300 0 103 +0.16 0 127 0 0 207 +0.16 0 217 +0.21 600 0 51 +0.16 0 63 0 0 103 +0.16 0 108 +0.21 1200 0 25 +0.16 0 31 0 0 51 +0.16 0 54 ?.70 2400 0 12 +0.16 0 15 0 0 25 +0.16 0 26 +1.14 4800 0 7 0 0 12 +0.16 0 13 ?.48 9600 0 3 0 19200 0 1 0 31250 0 1 0 38400 0 0 0 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w 265
table 14-3 examples of brr settings in asynchronous mode (2) xtal frequency (mhz) 4.9152 6 7.3728 8 bit error error error error rate n n (%) n n (%) n n (%) n n (%) 110 1 174 ?.26 2 52 +0.50 2 64 +0.70 2 70 +0.03 150 1 127 0 1 155 +0.16 1 191 0 1 207 +0.16 300 0 255 0 1 77 +0.16 1 95 0 1 103 +0.16 600 0 127 0 0 155 +0.16 0 191 0 0 207 +0.16 1200 0 63 0 0 77 +0.16 0 95 0 0 103 +0.16 2400 0 31 0 0 38 +0.16 0 47 0 0 51 +0.16 4800 0 15 0 0 19 ?.34 0 23 0 0 25 +0.16 9600 0 7 0 0 11 0 0 12 +0.16 19200 0 3 0 0 5 0 31250 0 2 0 0 3 0 38400 0 1 0 0 2 0 table 14-3 examples of brr settings in asynchronous mode (3) xtal frequency (mhz) 9.8304 10 12 12.288 bit error error error error rate n n (%) n n (%) n n (%) n n (%) 110 2 86 +0.31 2 88 ?.25 2 106 ?.44 2 108 +0.08 150 1 255 0 2 64 +0.16 2 77 0 2 79 0 300 1 127 0 1 129 +0.16 1 155 0 1 159 0 600 0 255 0 1 64 +0.16 1 77 0 1 79 0 1200 0 127 0 0 129 +0.16 0 155 +0.16 0 159 0 2400 0 63 0 0 64 +0.16 0 77 +0.16 0 79 0 4800 0 31 0 0 32 ?.36 0 38 +0.16 0 39 0 9600 0 15 0 0 15 +1.73 0 19 ?.34 0 19 0 19200 0 7 0 0 7 +1.73 0 9 0 31250 0 4 ?.70 0 4 0 0 5 0 0 5 +2.40 38400 0 3 0 0 3 +1.73 0 4 0 266
table 14-3 examples of brr settings in asynchronous mode (4) xtal frequency (mhz) 14.7456 16 19.6608 20 bit error error error error rate n n (%) n n (%) n n (%) n n (%) 110 2 130 ?.07 2 141 +0.03 2 174 ?.26 3 43 +0.88 150 2 95 0 2 103 +0.16 2 127 0 2 129 +0.16 300 1 191 0 1 207 +0.16 1 255 0 2 64 +0.16 600 1 95 0 1 103 +0.16 1 127 0 1 129 +0.16 1200 0 191 0 0 207 +0.16 0 255 0 1 64 +0.16 2400 0 95 0 0 103 +0.16 0 127 0 0 129 +0.16 4800 0 47 0 0 51 +0.16 0 63 0 0 64 +0.16 9600 0 23 0 0 25 +0.16 0 31 0 0 32 ?.36 19200 0 11 0 0 12 +0.16 0 15 0 0 15 +1.73 31250 0 7 0 0 9 ?.70 0 9 0 38400 0 5 0 0 7 0 0 7 +1.73 xtal frequency (mhz) 24 24.576 28 29.4912 32 bit error error error error error rate n n (%) n n (%) n n (%) n n (%) n n (%) 110 2 212 0.03 2 217 0.08 2 248 ?.17 3 64 0.70 3 70 0.03 150 2 155 0.16 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16 300 2 77 0.16 2 79 0.00 2 90 0.16 2 95 0.00 2 103 0.16 600 1 155 0.16 1 159 0.00 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 77 0.16 1 79 0.00 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 155 0.16 0 159 0.00 0 181 0.16 0 191 0.00 0 207 0.16 4800 0 77 0.16 0 79 0.00 0 90 0.16 0 95 0.00 0 103 0.16 9600 0 38 0.16 0 39 0.00 0 45 ?.93 0 47 0.00 0 51 0.16 19200 0 19 ?.34 0 19 0.00 0 22 ?.93 0 23 0.00 0 25 0.16 31250 0 11 0.00 0 11 2.40 0 13 0.00 0 14 ?.70 0 15 0.00 38400 0 9 ?.34 0 9 0.00 0 10 3.57 0 11 0.00 0 12 0.16 note: if possible, select a setting such that the error is 1% or less. b = osc 10 6 /[64 2 2n (n + 1)] b : bit rate n : brr value (0 n 255) osc : crystal oscillator frequency in mhz n : internal clock source (0, 1, 2, or 3) 267
the meaning of n is given by the table below: n cks1 cks0 clock 0 0 0 1 0 1 ?4 2 1 0 ?16 3 1 1 ?64 the error in asynchronous mode is calculated as follows: error (%) = osc 10 b 64 2 (n + 1) 2n } e1 100 6 { 268
table 14-4 examples of brr settings in synchronous mode xtal frequency (mhz) bit 2 4 8 10 16 20 32 rate n n n n n n n n n n n n n n 100 250 1 249 2 124 2 249 3 124 3 249 500 1 124 1 249 2 124 2 249 3 124 1k 0 249 1 124 1 249 2 124 2 249 2.5k 0 99 0 199 1 99 1 124 1 199 1 249 2 99 5k 0 49 0 99 0 199 0 249 1 99 1 124 1 199 10k 0 24 0 49 0 99 0 124 0 199 0 249 1 99 25k 0 9 0 19 0 39 0 49 0 79 0 99 0 159 50k 0 4 0 9 0 19 0 24 0 39 0 49 0 79 100k 0 4 0 9 0 19 0 24 0 39 250k 0 0 * 0 1 0 3 0 4 0 7 0 9 0 15 500k 0 0 * 0 1 0 3 0 4 0 7 1m 0 0 * 0 1 0 3 2.5m 0 0 * notes: blank: no setting is available. ? a setting is available, but the bit rate is inaccurate. * : continuous transfer is not possible. b = osc/[8 2 2n (n + 1)] b : bit rate n : brr value (0 n 255) osc : crystal oscillator frequency in mhz n : internal clock source (0, 1, 2, or 3) the meaning of n is given by the table below: n cks1 cks0 clock 0 0 0 1 0 1 ?4 2 1 0 ?16 3 1 1 ?64 269
14.3 operation 14.3.1 overview each serial communication interface channel supports serial data transfer in both asynchronous and synchronous modes. the communication format depends on settings in the smr as indicated in table 14-5. the clock source and usage of the sck pin depend on settings in the smr and scr as indicated in table 14-6. table 14-5 communication formats used by sci smr stop bit c/a chr pe stop mode format parity length 0 0 0 0 asynchronous 8-bit data none 1 1 2 1 0 yes 1 1 2 1 0 0 7-bit data none 1 1 2 1 0 yes 1 1 2 1 synchronous 8-bit data table 14-6 sci clock source selection smr scr clock c/a cke1 cke0 source sck pin 0 0 0 internal i/o port * (async 1 clock output at same frequency as baud rate mode) 1 0 external clock input at 16 times the baud rate frequency 1 1 0 0 internal serial clock output (sync 1 mode) 1 0 external serial clock input 1 * cannot be used by the sci. transmitting and receiving operations in the two modes are described next. 270
14.3.2 asynchronous mode in asynchronous mode, each character is individually synchronized by framing it with a start bit and stop bit. full duplex data transfer is possible because the sci has independent transmit and receive sections. double buffering in both sections enables the sci to be programmed for continuous data transfer. figure 14-2 shows the general format of one character sent or received in the asynchronous mode. the communication channel is normally held in the mark state (high). character transmission or reception starts with a transition to the space state (low). the first bit transmitted or received is the start bit (low). it is followed by the data bits, in which the least significant bit (lsb) comes first. the data bits are followed by the parity bit, if present, then the stop bit or bits (high) confirming the end of the frame. in receiving, the sci synchronizes on the falling edge of the start bit, and samples each bit at the center of bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate). 1. data format: table 14-7 lists the data formats that can be sent and received in asynchronous mode. eight formats can be selected by bits in the smr. start bit d0 d1 dn parity bit stop bit idle state one character 1 bit 7 or 8 bits 0 or 1 bit 1 or 2 bits figure 14-2 data format in asynchronous mode 271
table 14-7 data formats in asynchronous mode smr bits chr pe stop data format 0 0 0 start 8-bit data stop 0 0 1 start 8-bit data stop stop 0 1 0 start 8-bit data p stop 0 1 1 start 8-bit data p stop stop 1 0 0 start 7-bit data stop 1 0 1 start 7-bit data stop stop 1 1 0 start 7-bit data p stop 1 1 1 start 7-bit data p stop stop note: start: start bit stop: stop bit p: parity bit 2. clock: in the asynchronous mode it is possible to select either an internal clock created by the on-chip baud rate generator, or an external clock input at the sck pin. refer to table 14-6. if an external clock is input at the sck pin, its frequency should be 16 times the desired baud rate. if the internal clock provided by the on-chip baud rate generator is selected and the sck pin is used for clock output, the output clock frequency is equal to the baud rate, and the clock pulse rises at the center of the transmit data bits. figure 14-3 shows the phase relationship between the output clock and transmit data. fig. 14-3 output clock transmit data start bit d0 d1 d2 figure 14-3 phase relationship between clock output and transmit data 272
3. data transmission and reception sci initialization: before data can be transmitted or received, the sci must be initialized by software. to initialize the sci, software must clear the te and re bits to 0, then execute the following procedure. (1) set the desired communication format in the smr. (2) write the value corresponding to the desired bit rate in the brr. (this step is not necessary if an external clock is used.) (3) select the clock and enable desired interrupts in the scr. (4) set the te and/or re bit in the scr to 1. the te and re bits must both be cleared to 0 whenever the operating mode or data format is changed. after changing the operating mode or data format, before setting the te and re bits to 1 software must wait for at least the transfer time for 1 bit at the selected baud rate, to make sure the sci is initialized. if an external clock is used, the clock must not be stopped. when clearing the tdre bit during data transmission, to assure transfer of the correct data, do not clear the tdre bit until after writing data in the tdr. similarly, in receiving data, do not clear the rdrf bit until after reading data from the rdr. data transmission: the procedure for transmitting data is as follows. (1) set up the desired transmitting conditions in the smr, scr, and brr. (2) set the te bit in the scr to 1. the txd pin will automatically be switched to output and one frame* of all 1s will be transmitted, after which the sci is ready to transmit data. (3) check that the tdre bit is set to 1, then write the first byte of transmit data in the tdr. next clear the tdre bit to 0. * a frame is the data for one character, including the start bit and stop bit(s). 273
(4) the first byte of transmit data is transferred from the tdr to the tsr and sent in the designated format as follows. i) start bit (one 0 bit) ii) transmit data (seven or eight bits, starting from bit 0) iii) parity bit (odd or even parity bit, or no parity bit) iv) stop bit (one or two consecutive 1 bits) (5) transfer of the transmit data from the tdr to the tsr makes the tdr empty, so the tdre bit is set to 1. if the tie bit is set to 1, a transmit-end interrupt (txi) is requested. when the transmit function is enabled but the tdr is empty (tdre = 1), the output at the txd pin is held at 1 until the tdre bit is cleared to 0. data reception: the procedure for receiving data is as follows. (1) set up the desired receiving conditions in the smr, scr, and brr. (2) set the re bit in the scr to 1. the rxd pin will automatically be switched to input and the sci is ready to receive data. (3) the sci synchronizes with the incoming data by detecting the start bit, and places the received bits in the rsr. at the end of the data, the sci checks that the stop bit is 1. (4) when a complete frame has been received, the sci transfers the received data to the rdr so that it can be read. if the character length is 7 bits, the most significant bit of the rdr is cleared to 0. at the same time, the sci sets the rdrf bit in the ssr to 1. if the rie bit is set to 1, a receive-end interrupt (rxi) is requested. (5) the rdrf bit is cleared to 0 when the cpu reads the ssr, then writes a 0 in the rdrf bit, or when the rdr is read by the data transfer controller (dtc). the rdr is then ready to receive the next character from the rsr. when a frame is not received correctly, a receive error occurs. there are three types of receive errors, listed in table 14-8. if a receive error occurs, the rdrf bit in the ssr is not set to 1. the corresponding error flag is set to 1 instead. if the rie bit in the scr is set to 1, a receive-error interrupt (eri) is requested. 274
when a framing or parity error occurs, the rsr contents are transferred to the rdr. if an overrun error occurs, however, the rsr contents are not transferred to the rdr. if multiple receive errors occur simultaneously, all the corresponding error flags are set to 1. to clear a receive-error flag (orer, fer, or per), software must read the ssr, then write a 0 in the flag bit. table 14-8 receive errors name abbreviation description overrun error orer reception of the next frame ends while the rdrf bit is still set to 1. the rsr contents are not transferred to the rdr. framing error fer a stop bit is 0. the rsr contents are transferred to the rdr. parity error per the parity of a frame does not match the value selected by the bit in the smr. the rsr contents are transferred to the rdr. 14.3.3 synchronous mode the synchronous mode is suited for high-speed, continuous data transfer. each bit of data is synchronized with a serial clock pulse. continuous data transfer is enabled by the double buffering employed in both the transmit and receive sections of the sci. full duplex communication is possible because the transmit and receive sections are independent. 1. data format: figure 14-4 shows the communication format used in the synchronous mode. the data length is 8 bits for both the transmit and receive directions. the least significant bit (lsb) is sent and received first. each bit of transmit data is output from the falling edge of the serial clock pulse to the next falling edge. received bits are latched on the rising edge of the serial clock pulse. 275
2. clock: either the internal serial clock created by the on-chip baud rate generator or an external clock input at the sck pin can be selected in the synchronous mode. see table 14-6 for details. 3. data transmission and reception sci initialization: before data can be transmitted or received, the sci must be initialized by software. to initialize the sci, software must clear the te and re bits to 0 to disable both the transmit and receive functions, then execute the following procedure. (1) write the value corresponding to the desired bit rate in the brr. (this step is not necessary if an external clock is used.) (2) select the clock in the scr. (3) select the synchronous mode in the smr*. (4) set the te and/or re bit to 1, and enable desired interrupts in the scr. the te and re bits must both be cleared to 0 whenever the operating mode or data format is changed. after changing the operating mode or data format, before setting the te and re bits to 1 software must wait for at least 1 bit transfer time at the selected communication speed, to make sure the sci is initialized. * the sck pin is used for input or output according to the c/a bit in the serial mode register (smr) and the cke0 and cke1 bits in the serial control register (scr). (see table 14-6.) to prevent unwanted output at the sck pin, pay attention to the order in which you set smr and scr. data serial clock bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 don?-care transmission direction don?-care figure 14-4 data format in synchronous mode 276
when clearing the tdre bit during data transmission, to assure correct data transfer, do not clear the tdre bit until after writing data in the tdr. similarly, in receiving data, do not clear the rdrf bit until after reading data from the rdr. data transmission: the procedure for transmitting data is as follows. (1) set up the desired transmitting conditions in the smr, brr, and scr. (2) set the te bit in the scr to 1. the txd pin will automatically be switched to output, after which the sci is ready to transmit data. (3) check that the tdre bit is set to 1, then write the first byte of transmit data in the tdr. next clear the tdre bit to 0. (4) the first byte of transmit data is transferred from the tdr to the tsr and sent, each bit synchronized with a clock pulse. bit 0 is sent first. transfer of the transmit data from the tdr to the tsr makes the tdr empty, so the tdre bit is set to 1. if the tie bit is set to 1, a transmit-end interrupt (txi) is requested. the tdr and tsr function as a double buffer. continuous data transmission can be achieved by writing the next transmit data in the tdr and clearing the tdre bit to 0 while the sci is transmitting the current data from the tsr. if an internal clock source is selected, after transferring the transmit data from the tdr to the tsr, while transmitting the data from the tsr the sci also outputs a serial clock signal at the sck pin. when all data bits in the tsr have been transmitted, if the tdr is empty (tdre = 1), serial clock output is suspended until the next data byte is written in the tdr and the tdre bit is cleared to 0. during this interval the txd pin is held at the value of the last bit transmitted. if the external clock source is selected, data transmission is synchronized with the clock signal input at the sck pin. when all data bits in the tsr have been transmitted, if the tdr is empty (tdre = 1) but external clock pulses continue to arrive, the txd output remains high. data reception: the procedure for receiving data is as follows. (1) set up the desired receiving conditions in the smr, brr, and scr. 277
(2) set the re bit in the scr to 1. the rxd pin will automatically be switched to input and the sci is ready to receive data. (3) incoming data bits are latched in the rsr on eight clock pulses. when 8 bits of data have been received, the sci sets the rdrf bit in the ssr to 1. if the rie bit is set to 1, a receive-end interrupt (rxi) is requested. (4) the sci transfers the received data byte to the rdr so that it can be read. the rdrf bit is cleared when the program reads the rdrf bit in the ssr, then writes a 0 in the rdrf bit, or when the data transfer controller (dtc) reads the rdr. the rdr and rsr function as a double buffer. data can be received continuously by reading each byte of data from the rdr and clearing the rdrf bit to 0 before the last bit of the next byte is received. in general, an external clock source should be used for receiving data. if an internal clock source is selected, the sci starts receiving data as soon as the re bit is set to 1. the serial clock is also output at the sck pin. the sci continues receiving until the re bit is cleared to 0. if the last bit of the next data byte is received while the rdrf bit is still set to 1, an overrun error occurs and the orer bit is set to 1. if the rie bit is set to 1, a receive-error interrupt (eri) is requested. the data received in the rsr are not transferred to the rdr when an overrun error occurs. after an overrun error, reception of the next data is enabled when the orer bit is cleared to 0. simultaneous transmit and receive: the procedure for transmitting and receiving simultaneously is as follows: (1) set up the desired communication conditions in the smr, brr, and scr. (2) set the te and re bits in the scr to 1. the txd and rxd pins are automatically switched to output and input, respectively, and the sci is ready to transmit and receive data. (3) data transmitting and receiving start when the tdre bit in the ssr is cleared to 0. (4) data are sent and received in synchronization with eight clock pulses. 278
(5) first, the transmit data are transferred from the tdr to the tsr. this makes the tdr empty, so the tdre bit is set to 1. if the tie bit is set to 1, a transmit-end interrupt (txi) is requested. if continuous data transmission is desired, the cpu must read the tdre bit in the ssr, write the next transmit data in the tdr, then clear the tdre bit to 0. alternatively, the dtc can write the next transmit data in the tdr, in which case the tdre bit is cleared automatically. if the tdre bit is not cleared to 0 by the time the sci finishes sending the current byte from the tsr, the txd pin continues to output the last bit in the tsr. (6) in the receiving section, when 8 bits of data have been received they are transferred from the rsr to the rdr and the rdrf bit in the ssr is set to 1. if the rie bit is set to 1, a receive-end interrupt (rxi) is requested. (7) to clear the rdrf bit software read the rdrf bit in the ssr, read the data in the rdr, then write a 0 in the rdrf bit. alternatively, the dtc can read the rdr, in which case the rdrf bit is cleared automatically. for continuous data reception, the rdrf bit must be cleared to 0 before the last bit of the next byte of data is received. if the last bit of the next byte is received while the rdrf bit is still set to 1, an overrun error occurs. the error is handled as described under ?ata reception?above. 14.4 cpu interrupts and dtc interrupts the sci can request three types of interrupts: transmit-end (txi), receive-end (rxi), and receive-error (eri). interrupt requests are enabled or disabled by the tie and rie bits in the scr. independent signals are sent to the interrupt controller for each type of interrupt. the transmit-end and receive-end interrupt request signals are obtained from the tdre and rdrf flags. the receive-error interrupt request signal is the logical or of the three error flags: overrun error (orer), framing error (fer), and parity error (per). table 14-9 lists information about these interrupts. 279
table 14-9 sci interrupts dtc service interrupt description available? priority eri receive-error interrupt, requested when no high orer, fer, or per is set. rxi receive-end interrupt, requested when yes rdrf is set. txi transmit-end interrupt, requested when yes tdre is set. low the txi and rxi interrupts can be served by the data transfer controller (dtc) to have a data transfer performed. when the dtc serves one of these interrupts, it clears the tdre or rdrf bit to 0 under the following conditions, which differ between the two bits. when invoked by a txi request, if the dtc writes to the tdr, it automatically clears the tdre bit to 0. when invoked by an rxi request, if the dtc reads from the rdr, it automatically clears the rdrf bit to 0. see section 6, ?ata transfer controller?for further information on the dtc. 14.5 application notes application programmers should note the following features of the sci. 1. tdr write: the tdre bit in the ssr is simply a flag that indicates that the tdr contents have been transferred to the tsr. the tdr contents can be rewritten regardless of the tdre value. if a new byte is written in the tdr while the tdre bit is 0, before the old tdr contents have been moved into the tsr, the old byte will be lost. normally, software should check that the tdre bit is set to 1 before writing to the tdr. 2. multiple receive errors: table 14-10 lists the values of flag bits in the ssr when multiple receive errors occur, and indicates whether the rsr contents are transferred to the rdr. 280
table 14-10 ssr bit states and data transfer when multiple receive errors occur ssr bits receive error rdrf orer fer per rsr to rdr * 2 overrun error 1 * 1 1 0 0 no framing error 0 0 1 0 yes parity error 0 0 0 1 yes overrun + framing errors 1 * 1 1 1 0 no overrun + parity errors 1 * 1 1 0 1 no framing + parity errors 0 0 1 1 yes overrun + framing + parity errors 1 * 1 1 1 1 no notes: * 1 set to 1 before the overrun error occurs. * 2 yes: the rsr contents are transferred to the rdr. no: the rsr contents are not transferred to the rdr. 3. line break detection: when the rxd pin receives a continuous stream of 0s in the asynchronous mode (line-break state), a framing error occurs because the sci detects a 0 stop bit. the value h'00 is transferred from the rsr to the rdr. software can detect the line- break state as a framing error accompanied by h'00 data in the rdr. the sci continues to receive data, so if the fer bit is cleared to 0 another framing error will occur. 4. sampling timing and receive margin in asynchronous mode: the serial clock used by the sci in asynchronous mode runs at 16 times the bit rate. the falling edge of the start bit is detected by sampling the rxd input on the falling edge of this clock. after the start bit is detected, each bit of receive data in the frame (including the start bit, parity bit, and stop bit or bits) is sampled on the rising edge of the serial clock pulse at the center of the bit. see figure 14-5. it follows that the receive margin can be calculated as in equation (1). when the absolute frequency deviation of the clock signal is 0 and the clock duty factor is 0.5, data can theoretically be received with distortion up to the margin given by equation (2). this is a theoretical limit, however. in practice, system designers should allow a margin of 20% to 30%. 281
m = {(0.5 ?1/2n) ?(d ?0.5)/n ?(l ?0.5)f} 100 [%] (1) m: receive margin n: ratio of basic clock to bit rate (16) d: duty factor of clock?atio of high pulse width to low width (0.5 to 1.0) l: frame length (9 to 12) f: absolute clock frequency deviation when d = 0.5 and f= 0 m = (0.5 ?/2 16) 100 [%] = 46.875% (2) 5. note on transmitting in synchronous mode: when setting up serial communication interface 1 or 2 to transmit in synchronous mode, make sure the orer bit is cleared to 0. transmit operation will fail to start if the orer bit is set to 1. the same is true in simultaneous transmitting and receiving. basic clock receive data start bit sync sampling data sampling ?.5 pulses +7.5 pulses d0 d1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 figure 14-5 sampling timing (asynchronous mode) 282
section 15 a/d converter 15.1 overview the h8/534 and h8/536 have an analog-to-digital converter module which can be programmed for input of analog signal on up to eight channels. a/d conversion is performed by the successive approximations method with 10-bit resolution. 15.1.1 features the features of the on-chip a/d module are: eight analog input channels sample and hold circuit 10-bit resolution rapid conversion conversion time is 13.8 s per channel (at ?= 10 mhz) single and scan modes ?single mode: a/d conversion is performed once. ?scan mode: a/d conversion is performed in a repeated cycle on one to four channels. four 16-bit data registers these registers store a/d conversion results for up to four channels. a/d conversion can be started by external trigger input. a cpu interrupt (adi) can be requested at the completion of each a/d conversion cycle. this interrupt can also be served by the on-chip data transfer controller (dtc), providing a convenient way to move results into memory. 283
15.1.2 block diagram figure 15-1 shows a block diagram of a/d converter. fig. 15-1 av cc av ss an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 analog multiplexer sample & hold circuit + 10-bit d/a module data bus internal data bus control circuit ?8 ?16 adi interrupt signal addra: addrb: addrc: addrd: adcsr: adcr: a/d data register a a/d data register b a/d data register c a/d data register d a/d control/status register a/d control register successive approximations register addra addrb addrc addrd adcsr bus interface adtrg external trigger input adcr figure 15-1 block diagram of a/d converter 284
15.1.3 input pins table 15-1 lists the input pins used by the a/d converter module. the eight analog input pins are divided into two groups, consisting of analog inputs 0 to 3 (an 0 to an 3 ) and analog inputs 4 to 7 (an 4 to an 7 ), respectively. table 15-1 a/d input pins name abbreviation i/o function analog supply av cc input power supply and reference voltage for the voltage analog circuits. analog ground av ss input ground and reference voltage for the analog circuits. analog input 0 an 0 input analog input pins, group 0 analog input 1 an 1 input analog input 2 an 2 input analog input 3 an 3 input analog input 4 an 4 input analog input pins, group 1 analog input 5 an 5 input analog input 6 an 6 input analog input 7 an 7 input a/d external adtrg input external trigger input trigger input 15.1.4 register configuration table 15-2 lists the registers of the a/d converter module. table 15-2 a/d registers name abbreviation r/w initial value address a/d data register a (high) addra (h) r h'00 h'fee0 a/d data register a (low) addra (l) r h'00 h'fee1 a/d data register b (high) addrb (h) r h'00 h'fee2 a/d data register b (low) addrb (l) r h'00 h'fee3 a/d data register c (high) addrc (h) r h'00 h'fee4 a/d data register c (low) addrc (l) r h'00 h'fee5 a/d data register d (high) addrd (h) r h'00 h'fee6 a/d data register d (low) addrd (l) r h'00 h'fee7 a/d control/status register adcsr r/(w) * h'00 h'fee8 a/d control register adcr r/w h'7f h'fee9 * software can write 0 to clear the status flag bits but cannot write 1. 285
15.2 register descriptions 15.2.1 a/d data registers (addr)?'fee0 to h'fee7 the four a/d data registers (addra to addrd) are 16-bit read-only registers that store the results of a/d conversion. each result consist of 10 bits. the first 8 bits are stored in the upper byte of the data register corresponding to the selected channel. the last two bits are stored in the lower data register byte. each data register is assigned to two analog input channels as indicated in table 15-3. the a/d data registers are always readable by the cpu. the upper byte can be read directly. the lower byte is read via a temporary register. see section 15-3, ?pu interface?for details. the unused bits (bits 5 to 0) of the lower data register byte are always read as 0. the a/d data registers are initialized to h'0000 at a reset and in the standby modes. table 15-3 assignment of data registers to analog input channels analog input channel group 0 group 1 a/d data register an 0 an 4 addra an 1 an 5 addrb an 2 an 6 addrc an 3 an 7 addrd bit 7 6 5 4 3 2 1 0 addrn h ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r (n = a to d) bit 7 6 5 4 3 2 1 0 addrn h ad 1 ad 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r (n = a to d) 286
15.2.2 a/d control/status register (adcsr)?'fee8 * software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit. the a/d control/status register (adcsr) is an 8-bit readable/writable register that controls the operation of the a/d converter module. the adcsr is initialized to h'00 at a reset and in the standby modes. bit 7?/d end flag (adf): this status flag indicates the end of one cycle of a/d conversion. bit 7 adf description 0 this bit is cleared from 1 to 0 when: (initial value) 1. the chip is reset or placed in a standby mode. 2. the cpu reads the adf bit after it has been set to 1, then writes a 0 in this bit. 3. an a/d interrupt is served by the data transfer controller (dtc). 1 this bit is set to 1 at the following times: 1. single mode: when one a/d conversion is completed. 2. scan mode: when inputs on all selected channels have been converted. bit 6?/d interrupt enable (adie): this bit selects whether to request an a/d interrupt (adi) when a/d conversion is completed. bit 6 adie description 0 the a/d interrupt request (adi) is disabled. (initial value) 1 the a/d interrupt request (adi) is enabled. bit 7 6 5 4 3 2 1 0 adf adie adst scan cks ch2 ch1 ch0 initial value 0 0 0 0 0 0 0 0 read/write r/(w) * r/w r/w r/w r/w r/w r/w r/w 287
bit 5?/d start (adst): the a/d converter operates while this bit is set to 1. in the single mode, this bit is automatically cleared to 0 at the end of each a/d conversion. bit 5 adst description 0 a/d conversion is halted. (initial value) 1 1. single mode: one a/d conversion is performed. the adst bit is automatically cleared to 0 at the end of the conversion. 2. scan mode: a/d conversion starts and continues cyclically on the selected channels until the adst bit is cleared to 0. bit 4?can mode (scan): this bit selects the scan mode or single mode of operation. see section 15.4, ?peration?for descriptions of these modes. the mode should be changed only when the adst bit is cleared to 0. bit 4 scan description 0 single mode (initial value) 1 scan mode bit 3?lock select (cks): this bit controls the a/d conversion time. the conversion time should be changed only when the adst bit is cleared to 0. bit 3 cks description 0 conversion time = 274 states (maximum) (initial value) 1 conversion time = 138 states (maximum) bits 2 to 0?hannel select 2 to 0 (ch2 to ch0): these bits and the scan bit combine to select one or more analog input channels. the channel selection should be changed only when the adst bit is cleared to 0. 288
group select channel select selected channels ch2 ch1 ch0 single mode scan mode 0 0 0 an 0 an 0 0 1 an 1 an 0 and an 1 1 0 an 2 an 0 to an 2 1 1 an 3 an 0 to an 3 1 0 0 an 4 an 4 0 1 an 5 an 4 and an 5 1 0 an 6 an 4 to an 6 1 1 an 7 an 4 to an 7 15.2.3 a/d control register (adcr)?'fee9 the a/d control register (adcr) is an 8-bit readable/writable register that enables or disables the a/d external trigger signal. the adcr is initialized to h'7f at a reset and in the standby modes. bit 7?rigger enable (trge): this bit enables or disables the adtrg (a/d external trigger) signal. bit 7 trge description 0 external triggering of a/d conversion is disabled. (initial value) 1 a high-to-low transition of adtrg starts a/d conversion. bit 6 to 0?eserved: these bits cannot be modified and are always read as 1. bit 7 6 5 4 3 2 1 0 trge initial value 0 1 1 1 1 1 1 1 read/write r/w 289
15.3 cpu interface the a/d data registers (addra to addrd) are 16-bit registers. the upper byte of each register can be read directly, but the lower byte is accessed through an 8-bit temporary register (temp). when the cpu or dtc reads the upper byte of an a/d data register, at the same time as the upper byte is placed on the internal data bus, the lower byte is transferred to temp. when the lower byte is accessed, the value in temp is placed on the internal data bus. a program that requires all 10 bits of an a/d result should perform word access, or should read first the upper byte, then the lower byte of the a/d data register. either way, it is assured of obtaining consistent data. consistent data are not assured if the program reads the lower byte first. a program that requires only 8-bit a/d accuracy should perform byte access to the upper byte of the a/d data register. the value in temp can be left unread. figure 15-2 shows the data flow when the cpu (or dtc) reads an a/d data register. < lower byte read > cpu receives data h'40 bus interface module data bus < upper byte read > cpu receives data h'aa bus interface temp [h'40] addrn h [h'aa] addrn l [h'40] module data bus (n = a to d) temp [h'40] addrn h [h'aa] addrn l [h'40] (n = a to d) figure 15-2 read access to a/d data register (when register contains h'aa40) 290
15.4 operation the a/d converter performs 10 successive approximations to obtain a result ranging from h'0000 (corresponding to av ss ) to h'ffc0 (corresponding to av cc ). only the first 10 bits of the result are significant. the a/d converter module can be programmed to operate in single mode or scan mode as explained below. 15.4.1 single mode (scan = 0) the single mode is suitable for obtaining a single data value from a single channel. a/d conversion starts when the adst bit is set to 1. during the conversion process the adst bit remains set to 1. when conversion is completed, the adst bit is automatically cleared to 0. when the conversion is completed, the adf bit is set to 1. if the interrupt enable bit (adie) is also set to 1, an a/d conversion end interrupt (adi) is requested, so that the converted data can be processed by an interrupt-handling routine. alternatively, the interrupt can be served by the data transfer controller (dtc). when an a/d interrupt is served by the dtc, the dtc automatically clears the adf bit to 0. when an a/d interrupt is served by the cpu, however, the adf bit remains set until the cpu reads the adcsr, then writes a 0 in the adf bit. before selecting the single mode, clock, and analog input channel, software should clear the adst bit to 0 to make sure the a/d converter is stopped. changing the mode, clock, or channel selection while a/d conversion is in progress can lead to conversion errors. the following example explains the a/d conversion process in single mode when channel 1 (an 1 ) is selected. figure 15-3 shows the corresponding timing chart. 1. software clears the adst bit to 0, then selects the single mode (scan = 0) and channel 1 (ch2 to ch0 = ?01?, enables the a/d interrupt request (adie = 1), and sets the adst bit to 1 to start a/d conversion. (selection of mode, clock channel and setting the adst bit can be done at same time.) coding example: (when using the slow clock, cks = 0) bclr #5, @h'fee8 mov.b #h'61, @h'fee8 2. the a/d converter samples the an 1 input and converts the voltage level to a digital value. at the end of the conversion process the a/d converter transfers the result to register addrb, sets the adf bit is set to 1, clears the adst bit to 0, and halts. 291
3. adf = 1 and adie = 1, so an a/d interrupt is requested. 4. the user-coded a/d interrupt-handling routine is started. 5. the interrupt-handling routine reads the adcsr value, then writes a 0 in the adf bit to clear this bit to 0. 6. the interrupt-handling routine reads and processes the a/d conversion result. 7. the routine ends. steps 2 to 7 can now be repeated by setting the adst bit to 1 again. if the data transfer enable (dte) bit is set to 1, the interrupt is served by the data transfer controller (dtc). steps 4 to 7 then change as follows. 4? the dtc is started. 5? the dtc automatically clears the adf bit to 0. 6? the dtc transfers the a/d conversion result from addrb to a specified destination address. 7? the dtc ends. 292
interrupt (adi) adie adst adf channel 0 (an ) 0 channel 1 (an ) 1 channel 2 (an ) 2 channel 3 (an ) 3 addra addrb addrc addrd indicates execution of a software instruction set waiting waiting waiting waiting a/d conver- sion a/d conver- sion waiting a/d conversion result a/d conversion result waiting a/d conversion starts set set clear clear read result read result * * * * * * figure 15-3 a/d operation in single mode (when channel 1 is selected) 293
15.4.2 scan mode (scan = 1) the scan mode can be used to monitor analog inputs on one or more channels. when the adst bit is set to 1, a/d conversion starts from the first channel selected by the ch bits. when ch2 = 0 the first channel is an 0 . when ch2 = 1 the first channel is an 4 . if the scan group includes more than one channel (i.e. if bit ch1 or ch0 is set), conversion of the next channel begins as soon as conversion of the first channel ends. conversion of the selected channels continues cyclically until the adst bit is cleared to 0. the conversion results are placed in the data registers corresponding to the selected channels. before selecting the scan mode, clock, and analog input channels, software should clear the adst bit to 0 to make sure the a/d converter is stopped. changing the mode, clock, or channel selection while a/d conversion is in progress can lead to conversion errors. the following example explains the a/d conversion process when three channels in group 0 are selected (an 0 , an 1 , and an 2 ). figure 15-4 shows the corresponding timing chart. 1. software clears the adst bit to 0, then selects the scan mode (scan = 1), scan group 0 (ch2 = 0), and analog input channels an 0 to an 2 (ch1 and ch0 = 0) and sets the adst bit to 1 to start a/d conversion. coding example: (with slow clock and adi interrupt enabled) bclr #5, @h'fee8 mov.b #h'72, @fee8 2. the a/d converter samples the input at an 0 , converts the voltage level to a digital value, and transfers the result to register addra. 3. next the a/d converter samples and converts an 1 and transfers the result to addrb. then it samples and converts an 2 and transfers the result to addrc. 4. after all selected channels (an 0 to an 2 ) have been converted, the ad converter sets the adf bit to 1. if the adie bit is set to 1, an a/d interrupt (adi) is requested. then the a/d converter begins converting an 0 again. 5. steps 2 to 4 are repeated cyclically as long as the adst bit remains set to 1. to stop the a/d converter, software must clear the adst bit to 0. 294
fig. 15-4 adst adf channel 3 (an ) 3 channel 0 (an ) 0 channel 1 (an ) 1 channel 2 (an ) 2 addra addrb addrc addrd indicates execution of a software instruction waiting waiting waiting set continuous a/d conversion transfer a/d conver- sion waiting a/d conver- sion ? a/d conversion time clear clear a/d conver- sion a/d conver- sion a a/d conver- sion waiting a/d conversion ? a/d conversion a/d conversion a a/d conver- sion ? waiting waiting waiting waiting * * * * figure 15-4 a/d operation in scan mode (when channels 0 to 2 are selected) 295
15.4.3 input sampling time and a/d conversion time the a/d converter includes a built-in sample-and-hold circuit. sampling of the input starts at a time t d after the adst bit is set to 1. the sampling process lasts for a time t spl . the actual a/d conversion begins after sampling is completed. figure 15-5 shows the timing of these steps, and table 15-4 lists the total conversion times (t conv ) for the single mode. the total conversion time includes t d and t spl . the purpose of t d is to synchronize the adcsr write time with the a/d conversion process, so the length of t d is variable. the total conversion time therefore varies within the minimum to maximum ranges indicated in table 15-4. in the scan mode, the ranges given in table 15-4 apply to the first conversion. the length of the second and subsequent conversion processes is fixed at 256 states (when cks = 0) or 128 states (when cks = 1). internal address bus write signal input sampling timing adf (1) (2) t d t spl t conv (1) (2) t t t : adcsr write cycle : adcsr address : synchronization delay : input sampling time : total a/d conversion time d spl conv figure 15-5 a/d conversion timing 296
table 15-4 a/d conversion time (single mode) cks = 0 cks = 1 item symbol min typ max min typ max synchronization delay t d 18 33 10 17 input sampling time t spl 63 31 total a/d conversion time t conv 259 274 131 138 note: values in the table are numbers of states. 15.4.4 external triggering of a/d conversion a/d conversion can be started by an external trigger input. external trigger input is enabled at the adtrg pin when the trge bit in the adcr is set to 1. between 1.5 and 2 ?clock cycles after the adtrg input goes low, the adst bit in the adcsr is set to 1 and a/d conversion commences. the timing of external triggering is shown in figure 15-6. adst adtrg a/d conversion 1.0 to 2.0 cycles figure 15-6 timing of setting of adst bit 297
15.5 interrupts and the data transfer controller the adi interrupt request is enabled or disabled by the adie bit in the adcsr. when the adi bit in data transfer enable register dtef (bit 4 at address h'ff0d) is set to 1, the adi interrupt is served by the data transfer controller. the dtc can be used to transfer a/d results to a buffer in memory, or to an i/o port. the dtc automatically clears the adf bit to 0. note: in scan mode, the dtc can transfer data for only one channel per interrupt, even if two or more channels are selected. 298
section 16 ram 16.1 overview the h8/534 and h8/536 include 2 kbytes of on-chip static ram, connected to the cpu by a 16-bit data bus. both byte and word access to the on-chip ram are performed in two states, enabling rapid data transfer and instruction execution. the on-chip ram is assigned to addresses h'f680 to h'fe7f in the chips address space. a ram control register (ramcr) can enable or disable the on-chip ram, permitting these addresses to be allocated to external memory instead, if so desired. 16.1.1 block diagram figure 16-1 shows the block diagram of the on-chip ram. internal data bus (upper 8 bits) internal data bus (lower 8 bits) on-chip ram address h'f680 h'f682 h'fe7e ramcr even addresses odd addresses ramcr: ram control register figure 16-1 block diagram of on-chip ram 299
16.1.2 register configuration the on-chip ram is controlled by the register described in table 16-1. table 16-1 ram control register name abbreviation r/w initial value address ram control register ramcr r/w h'ff h'ff11 16.2 ram control register (ramcr) the ram control register (ramcr) is an 8-bit register that enables or disable the on-chip ram. bit 7?am enable (rame): this bit enables or disables the on-chip ram. the rame bit is initialized on the rising edge of the reset signal. it is not initialized in the software standby mode. bit 7 rame description 0 on-chip ram is disabled. 1 on-chip ram is enabled. (initial value) bits 6 to 0?eserved: these bits cannot be modified and are always read as 1. 16.3 operation 16.3.1 expanded modes (modes 1, 2, 3, and 4) if the rame bit is set to 1, accesses to addresses h'f680 to h'fe7f are directed to the on-chip ram. if the rame bit is cleared to 0, accesses to addresses h'f680 to h'fe7f are directed to the external data bus. bit 7 6 5 4 3 2 1 0 rame initial value 1 1 1 1 1 1 1 1 read/write r/w 300
16.3.2 single-chip mode (mode 7) if the rame bit is set to 1, accesses to addresses h'f680 to h'fe7f are directed to the on-chip ram. if the rame bit is cleared to 0, access of any type (instruction fetch or data read or write) to addresses h'f680 to h'fe7f causes an address error and initiates the cpus exception-handling sequence. 301
section 17 rom 17.1 overview the h8/534 includes 32 kbytes of high-speed, on-chip rom. the h8/536 has 62 kbytes of on- chip rom. the on-chip rom is connected to the cpu via a 16-bit data bus and is accessed in two states. users wishing to program the chip themselves can request electrically programmable rom (prom). the prom version has a prom mode in which the chip can be programmed with a standard, external prom writer. the chip is also available with masked rom. the on-chip rom is enabled or disabled depending on the mcu operating mode, which is determined by the inputs at the mode pins when the chip comes out of the reset state. see table 17-1. table 17-1 rom usage in each mcu mode mode pins mode md 2 md 1 md 0 rom mode 1 (expanded minimum mode) 0 0 1 disabled (external addresses) mode 2 (expanded minimum mode) 0 1 0 enabled mode 3 (expanded maximum mode) 0 1 1 disabled (external addresses) mode 4 (expanded maximum mode) 1 0 0 enabled mode 7 (single-chip mode) 1 1 1 enabled 17.1.1 block diagram figure 17-1 shows the block diagram of the on-chip rom. 303
17.2 prom mode 17.2.1 prom mode setup the prom version has a prom mode in which the usual microcomputer functions of the h8/534 or h8/536 are halted to allow the on-chip prom to be programmed. to select the prom mode, apply the signal inputs listed in table 17-2. table 17-2 selection of prom mode pin input mode pins (md 2 , md 1 , and md 0 ) low stby pin low p6 1 and p6 0 high internal data bus (upper 8 bits) internal data bus (lower 8 bits) on-chip rom addresses h8/534 h'0002 h'7ffe even addresses odd addresses h'0000 h8/536 h'0002 h'f67e h'0000 figure 17-1 block diagram of on-chip rom 304
17.2.2 socket adapter pin arrangements and memory map the h8/534 or h8/536 can be programmed with a general-purpose prom writer by attaching a socket adapter as listed in table 17-3. the socket adapter depends on the type of package. figure 17-2(a) and (b) show the socket adapter pin arrangements. figure 17-3 is a memory map. table 17-3 socket adapter chip package socket adapter h8/534 84-pin plcc (cp-84) hs538esc01h 84-pin windowed lcc (cg-84) hs538esg01h 80-pin qfp (fp-80a) hs538esh01h 80-pin tqfp (tfp-80c) hs5348esn01h * h8/536 84-pin plcc (cp-84) hs538esc02h 84-pin windowed lcc (cg-84) hs538esg02h 80-pin qfp (fp-80a) hs538esh02h 80-pin tqfp (tfp-80c) hs5368esn01h * note: * under development. 305
v pp: programming power (12.5 v) e 7 to e 0 : data input/output ea 14 to ea 0 : address input oe: output enable ce: chip enable note: all pins not shown in this figure should be left open. h8/534 pin hn27c256 (28 pins) v pp 1 ea 9 24 eo 0 11 eo 1 12 eo 2 13 eo 3 15 eo 4 16 eo 5 17 eo 6 18 eo 7 19 ea 0 10 ea 1 9 ea 2 8 ea 3 7 ea 4 6 ea 5 5 ea 6 4 ea 7 3 ea 8 25 oe 22 ea 10 21 ea 11 23 ea 12 2 ea 13 26 ea 14 27 ce 20 v cc 28 vss 14 eprom socket fp-80a cg-84, cp-84 pin 10 21 res 11 22 nmi 13 25 p3 0 14 26 p3 1 15 27 p3 2 16 28 p3 3 17 29 p3 4 18 30 p3 5 19 31 p3 6 20 32 p3 7 21 33 p4 0 22 34 p4 1 23 35 p4 2 24 36 p4 3 25 37 p4 4 26 38 p4 5 27 39 p4 6 28 40 p4 7 30 43 p5 0 31 44 p5 1 32 45 p5 2 33 46 p5 3 34 47 p5 4 35 48 p5 5 36 49 p5 6 37 50 p5 7 38 51 p6 0 39 52 p6 1 60 74 av cc 5 16 v cc 42 55 v cc 6 17 md 0 7 18 md 1 8 19 md 2 9 20 stby 51 65 av ss 12 2 v ss 29 24 v ss 71 41 v ss 42 v ss 64 v ss 83 v ss figure 17-2(a) socket adapter pin arrangements (h8/534) 306
v pp: programming power (12.5 v) e 7 to e 0 : data input/output ea 16 to ea 0 : address input oe: output enable ce: chip enable pgm : program note: all pins not shown in this figure should be left open. h8/536 pin hn27c101 (32 pins) v pp 1 ea 9 26 ea 15 3 ea 16 2 pgm 31 eo 0 13 eo 1 14 eo 2 15 eo 3 17 eo 4 18 eo 5 19 eo 6 20 eo 7 21 ea 0 12 ea 1 11 ea 2 10 ea 3 9 ea 4 8 ea 5 7 ea 6 6 ea 7 5 ea 8 27 oe 24 ea 10 23 ea 11 25 ea 12 4 ea 13 28 ea 14 29 ce 22 v cc 32 v ss 16 eprom socket fp-80a cg-84, cp-84 pin 10 21 res 11 22 nmi 76 7 p1 4 77 8 p1 5 78 9 p1 6 13 25 p3 0 14 26 p3 1 15 27 p3 2 16 28 p3 3 17 29 p3 4 18 30 p3 5 19 31 p3 6 20 32 p3 7 21 33 p4 0 22 34 p4 1 23 35 p4 2 24 36 p4 3 25 37 p4 4 26 38 p4 5 27 39 p4 6 28 40 p4 7 30 43 p5 0 31 44 p5 1 32 45 p5 2 33 46 p5 3 34 47 p5 4 35 48 p5 5 36 49 p5 6 37 50 p5 7 38 51 p6 0 39 52 p6 1 60 74 av cc 5 16 v cc 42 55 v cc 6 17 md 0 7 18 md 1 8 19 md 2 9 20 stby 51 65 av ss 12 2 v ss 29 24 v ss 71 41 v ss 42 v ss 64 v ss 83 v ss figure 17-2(b) socket adapter pin arrangements (h8/536) 307
17.3 h8/534 programming the write, verify, and inhibited sub-modes of the prom mode are selected as shown in table 17-4. table 17-4 selection of sub-modes in prom mode (h8/534) pins mode ce oe v pp v cc 0 7 to 0 0 a 14 to a 0 write low high v pp v cc data input address input verify high low v pp v cc data output address input programming inhibited high high v pp v cc high-impedance address input note: the v pp and v cc pins must be held at the v pp and v cc voltage levels. the h8/534 prom uses the same, standard read/write specifications as the hn27c256 and hn27256. 17.3.1 writing and verifying an efficient, high-speed programming procedure can be used to write and verify prom data. this procedure writes data quickly without subjecting the chip to voltage stress and without sacrificing data reliability. it leaves the data h'ff written in unused addresses. h8/536 on-chip rom address in mcu mode address in mcu mode address in prom mode address in prom mode h'0000 h'0000 h'0000 h'0000 h'7fff * in mode 2, h'ee80 to h'f67f are external addresses. do not attempt to program these addresses if the h8/536 will be used in mode 2. h'f67f h'ee80 * h'7fff h'f67f h8/534 on-chip rom figure 17-3 memory map in prom mode 308
figure 17-4 shows the basic high-speed programming flowchart. tables 17-5 and 17-6 list the electrical characteristics of the chip in the prom mode. figure 17-5 shows a write/verify timing chart. set prog./verify mode v = 6.0 v ?.25 v, v = 12.5 v ?.5 v address = 0 n = 0 n + 1 n program tpw = 1 ms ?% verify n n y go n < s s = 25 address + 1 address last address? n y program topw = 3n ms set read mode v = 5.0 v, v = v read all addresses end nogo go fail start cc pp cc pp cc figure 17-4 high-speed programming flowchart (h8/534) 309
table 17-5 dc characteristics (h8/534) (when v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, v ss = 0 v, ta = 25?c 5?c) sym- measurement item bol min typ max unit conditions input high voltage o 7 to o 0 , a 14 to a 0 , oe, ce v ih 2.4 v cc + 0.3 v input low voltage o 7 to o 0 , a 14 to a 0 , oe, ce v il ?.3 0.8 v input high voltage o 7 to o 0 v oh 2.4 v i oh = ?00 a input low voltage o 7 to o 0 v ol 0.45 v i ol = 1.6 ma input leakage o 7 to o 0 , a 14 to a 0 , oe, ce |i li | 2 a v in = current 5.25 v/0.5 v v cc current i cc 40 ma v pp current i pp 40 ma table 17-6 ac characteristics (h8/534) (when v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, ta = 25?c 5?c) sym- measurement item bol min typ max unit conditions address setup time t as 2 s see figure oe setup time t oes 2 s 17-5 * data setup time t ds 2 s address hold time t ah 0 s data hold time t dh 2 s data output disable time t df 130 ns v pp setup time t vps 2 s program pulse width t pw 0.95 1.0 1.05 ms oe pulse width for t opw 2.85 78.75 ms overwrite-programming v cc setup time t vcs 2 s data output delay time t oe 0 500 ns * input pulse level: 0.8 v to 2.2 v input rise/fall time 20 ns timing reference levels: input?.0 v, 2.0 v; output?.8 v, 2.0 v 310
17.3.2 notes on writing 1. write with the specified voltages and timing. the programming voltage (v pp ) in the prom mode is 12.5 v. caution: applied voltages in excess of the specified values can permanently destroy to the chip. be particularly careful about the prom writers overshoot characteristics. if the prom writer is set to intel specifications or hitachi hn27256 or hn27c256 specifications, vpp will be 12.5 v. 2. before writing data, check that the socket adapter and chip are correctly mounted in the prom writer. overcurrent damage to the chip can result if the index marks on the prom writer, socket adapter, and chip are not correctly aligned. address t as write verify data v pp v pp v cc v cc v cc v cc +1 ce oe input data output data t ds t dh t vps t vcs t ah t df t pw t oes t oe figure 17-5 prom write/verify timing (h8/534) 311
3. don? touch the socket adapter or chip while writing. touching either of these can cause contact faults and write errors. 17.4 h8/536 programming the write, verify, and other sub-modes of prom mode are selected as shown in table 17-7. table 17-7 selection of sub-modes in prom mode (h8/536) pins mode ce oe pgm v pp v cc 0 7 to 0 0 a 16 to a 0 write low high low v pp v cc data input address input verify low low high v pp v cc data output address input programming inhibited low low low v pp v cc high-impedance address input low high high high low low high high high note: the v pp and v cc pins must be held at the v pp and v cc voltage levels. standard eprom read/write specifications are used, the same as for the hn27c101. the hn27c101 has two programming modes: page programming and byte programming. the h8/536 does not support page programming, so select byte programming. 17.4.1 writing and verifying an efficient, high-speed programming procedure can be used to write and verify prom data. this procedure writes data quickly without subjecting the chip to voltage stress and without sacrificing data reliability. it leaves the data h'ff written in unused addresses. figure 17-6 shows the basic high-speed programming flowchart. tables 17-8 and 17-9 list the electrical characteristics of the chip during programming. figure 17-7 shows a timing diagram. 312
set prog./verify mode v = 6.0 v ?.25 v, v = 12.5 v ?.3 v address = 0 n = 0 n + 1 n program tpw = 0.2 ms ?% verify n n y go n < s s = 25 address + 1 address last address? n y program topw = 0.2n ms set read mode v = 5.0 v, v = v read all addresses end nogo go fail start cc pp cc pp cc figure 17-6 high-speed programming flowchart (h8/536) 313
table 17-8 dc characteristics (h8/536) (when v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, v ss = 0 v, ta = 25?c 5?c) sym- test item bol min typ max unit conditions input high voltage o 7 to o 0 , a 16 to a 0 , oe, v ih 2.4 v cc + 0.3 v ce, pgm input low voltage o 7 to o 0 , a 16 to a 0 , oe, v il ?.3 0.8 v ce, pgm output high voltage o 7 to o 0 v oh 2.4 v i oh = ?00 a output low voltage o 7 to o 0 v ol 0.45 v i ol = 1.6 ma input leakage o 7 to o 0 , a 16 to a 0 , oe, |i li | 2 a v in = 5.25 v/ current ce, pgm 0.5 v v cc current i cc 40 ma v pp current i pp 40 ma table 17-9 ac characteristics (h8/536) (when v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, ta = 25?c 5?c) sym- test item bol min typ max unit conditions address setup time t as 2 s see figure oe setup time t oes 2 s 17-7 * data setup time t ds 2 s address hold time t ah 0 s data hold time t dh 2 s data output disable time t df 130 ns v pp setup time t vps 2 s program pulse width t pw 0.19 0.20 0.21 ms oe pulse width for t opw 0.19 5.25 ms overwrite-programming v cc setup time t vcs 2 s oe setup time t ces 2 s data output delay time t oe 0 150 ns * input pulse level: 0.8 v to 2.2 v input rise/fall time 20 ns timing reference levels: input?.0 v, 2.0 v; output?.8 v, 2.0 v 314
17.4.2 notes on programming 1. program with the specified voltages and timing. the programming voltage (v pp ) in prom mode is 12.5 v. caution: applied voltages in excess of the specified values can permanently destroy the chip. be particularly careful about the prom writers overshoot characteristics. if the prom writer is set to hitachi hn27c101 specifications, v pp will be 12.5 v. 2. before programming, check that the socket adapter and chip are correctly mounted in the prom writer. overcurrent damage to the chip can result if the index marks on the prom writer, socket adapter, and chip are not correctly aligned. address t as write verify data v pp v pp v cc v cc v cc v cc +1 ce oe input data output data t ds t dh t vps t vcs t ah t df t pw t oes t oe t ces pgm figure 17-7 prom write/verify timing (h8/536) 315
3. don? touch the socket adapter or chip while programming. touching either of these can cause contact faults and write errors. 4. the h8/536 uses the hn27c101s byte programming mode. note that some prom writers do not support the hn27c101s byte programming mode. table 17-10 lists the prom writers recommended for use with the hd6475368r. table 17-10 prom writers recommended prom writers vendor model data i/o 29b + unipak 2b v21.0 * 212 v2.0 * 288a v4.1 * si000 v15.0 * unisite 40 v3.0 * 2900 v1.0 * aval data pkw-3100 pkw-1100 minato electronics model 1892 80-pin qfp type: ga91-15 84-pin plcc type: ga91-16 model 1891 80-pin qfp type: ga91-15 84-pin plcc type: ga91-16 note: * use prom writers with the indicated or higher version numbers. 5. the h8/536 prom size is 62 kbytes. when programming, leave data h'ff in addresses h'f680 to h'1ffff. 316
17.5 reliability of written data an effective way to assure the data holding characteristics of the programmed chips is to bake them at 150?c, then screen them for data errors. this procedure quickly eliminates chips with prom memory cells prone to early failure. figure 17-8 shows the recommended screening procedure. if a series of write errors occur while the same prom writer is in use, stop programming and check the prom writer and socket adapter for defects, using a microcomputer with a windowed package and on-chip eprom. please inform hitachi of any abnormal conditions noted during programming or in screening of program data after high-temperature baking. figure 17-8 recommended screening procedure write program bake with power off 150 c 48 hr read and check program v cc = 5.0 v install 317
17.6 erasing of data the windowed package enables data to be erased by illuminating the window with ultraviolet light. table 17-11 lists the erasing conditions. table 17-11 erasing conditions item value ultraviolet wavelength 253.7 nm minimum illumination 15 w?/cm 2 the conditions in table 17-11 can be satisfied by placing a 12000-w/cm 2 ultraviolet lamp 2 or 3 centimeters directly above the chip and leaving it on for about 20 minutes. 318
17.7 handling of windowed packages 1. glass erasing window: rubbing the glass erasing window of a windowed package with a plastic material or touching it with an electrically charged object can create a static charge on the window surface which may cause the chip to malfunction. if the erasing window becomes charged, the charge can be neutralized by a short exposure to ultraviolet light. this returns the chip to its normal condition, but it also reduces the charge stored in the floating gates of the prom, so it is recommended that the chip be reprogrammed afterward. accumulation of static charge on the window surface can be prevented by the following precautions: (1) when handling the package, ground yourself. dont wear gloves. avoid other possible sources of static charge. (2) avoid friction between the glass window and plastic or other materials that tend to accumulate static charge. (3) be careful when using cooling sprays, since they may have a slight ion content. (4) cover the window with an ultraviolet-shield label, preferably a label including a conductive material. besides protecting the prom contents from ultraviolet light, the label protects the chip by distributing static charge uniformly. 2. handling after programming: fluorescent light and sunlight contain small amounts of ultraviolet, so prolonged exposure to these types of light can cause programmed data to invert. in addition, exposure to any type of intense light can induce photoelectric effects that may lead to chip malfunction. it is recommended that after programming the chip, you cover the erasing window with a light-proof label (such as an ultraviolet-shield label). 3. 84-pin lcc package mounting: when mounted on a printed circuit board, the 84-pin lcc package must be mounted in a socket. the recommended socket is listed in table 17-12. table 17-12 socket for 84-pin lcc package manufacturer product code sumitomo 3-m 284-1273-00-1102j 319
section 18 power-down state 18.1 overview the h8/534 and h8/536 have a power-down state that greatly reduces power consumption by stopping the cpu functions. the power-down state includes three modes: 1. sleep mode a software-triggered mode in which the cpu halts but the rest of the chip remains active 2. software standby mode a software-triggered mode in which the entire chip is inactive 3. hardware standby mode a hardware-triggered mode in which the entire chip is inactive the sleep mode and software standby mode are entered from the program execution state by executing the sleep instruction under the conditions given in table 18-1. the hardware standby mode is entered from any other state by a low input at the stby pin. table 18-1 lists the conditions for entering and leaving the power-down modes. it also indicates the status of the cpu, on-chip supporting modules, etc., in each power-down mode. table 18-1 power-down state entering cpu sup. i/o exiting mode procedure clock cpu regs. mods. ram ports methods sleep execute run halt held run held held ?interrupt mode sleep ?res low instruction ?stby low soft- set ssby bit halt halt held halt held held ?nmi ware in sbycr to and ?res low standby 1, then initialized ?stby low mode execute sleep instruction * hard- set stby halt halt not halt held high ?stby high, ware pin to low held and impe- then res standby level initialized dance low ? high mode state * the watchdog timer must also be stopped. notes: sbycr software standby control register ssby software standby bit 321
18.2 sleep mode 18.2.1 transition to sleep mode execution of the sleep instruction causes a transition from the program execution state to the sleep mode. after executing the sleep instruction, the cpu halts, but the contents of its internal registers remain unchanged. the functions of the on-chip supporting modules do not stop in the sleep mode. 18.2.2 exit from sleep mode the chip wakes up from the sleep mode when it receives an internal or external interrupt request, or a low input at the res or stby pin. 1. wake-up by interrupt: an interrupt releases the sleep mode and starts either the cpus interrupt-handling sequence or the data transfer controller (dtc). if the interrupt is served by the dtc, after the data transfer is completed the cpu executes the instruction following the sleep instruction, unless the count in the data transfer count register (dtcr) is 0. if an interrupt on a level equal to or less than the mask level in the cpus status register (sr) is requested, the interrupt is left pending and the sleep mode continues. also, if an interrupt from an on-chip supporting module is disabled by the corresponding enable/disable bit in the modules control register, the interrupt cannot be requested, so it cannot wake the chip up. 2. wake-up by res pin: when the res pin goes low, the chip exits from the sleep mode to the reset state. 3. wake-up by stby pin: when the stby pin goes low, the chip exits from the sleep mode to the hardware standby mode. 18.3 software standby mode 18.3.1 transition to software standby mode a program enters the software standby mode by setting the standby bit (ssby) in the software standby control register (sbycr) to 1, then executing the sleep instruction. table 18-2 lists the attributes of the software standby control register. 322
table 18-2 software standby control register name abbreviation r/w initial value address software standby control register sbycr r/w h'7f h'ff13 in the software standby mode, the cpu, clock, and the on-chip supporting module functions all stop, reducing power consumption to an extremely low level. the on-chip supporting modules and their registers are reset to their initial state, but as long as a minimum necessary voltage supply is maintained (at least 2 v), the contents of the cpu registers and on-chip ram remain unchanged. the i/o ports also remain in their current states. 18.3.2 software standby control register (sbycr) the software standby control register (sbycr) is an 8-bit register that controls the action of the sleep instruction. bit 7?oftware standby (ssby): this bit enables or disables the transition to the software standby mode. bit 7 ssby description 0 the sleep instruction causes a transition to the sleep mode. (initial value) 1 the sleep instruction causes a transition to the software standby mode. the watchdog timer must be stopped before the chip can enter the software standby mode. to stop the watchdog timer, clear the timer enable bit (tme) in the watchdog timers timer control/status register (tcsr) to 0. the ssby bit cannot be set to 1 while the tme bit is set to 1. when the chip is recovered from the software standby mode by a nonmaskable interrupt (nmi), the ssby bit is automatically cleared to 0. it is also cleared to 0 by a reset or transition to the hardware standby mode. bits 6 to 0?eserved: these bits cannot be modified and are always read as 1. bit 7 6 5 4 3 2 1 0 ssby initial value 0 1 1 1 1 1 1 1 read/write r/w 323
18.3.3 exit from software standby mode the chip can be brought out of the software standby mode by an input at one of three pins: the nmi pin, res pin, or stby pin. 1. recovery by nmi pin: when an nmi request signal is received, the clock oscillator begins operating but clock pulses are supplied only to the watchdog timer (wdt). the watchdog timer begins counting from h'00 at the rate determined by the clock select bits (cks2 to cks0) in its timer status/control register (tcsr). this rate should be set slow enough to allow the clock oscillator to stabilize before the count reaches h'ff. when the count overflows from h'ff to h'00, clock pulses are supplied to the whole chip, the software standby mode ends, and execution of the nmi interrupt-handling sequence begins. the clock select bits (cks2 to cks0) should be set as follows. (1) crystal oscillator: set cks2 to cks0 to a value that makes the watchdog timer interval equal to or greater than 10ms, which is the clock stabilization time. (2) external clock input: cks2 to cks0 can be set to any value. the minimum value (cks2 = cks1 = cks0 = 0) is recommended. 2. recovery by res pin: when the res pin goes low, the clock oscillator starts. next, when the res pin goes high, the cpu begins executing the reset sequence. when the chip recovers from the software standby mode by a reset, clock pulses are supplied to the entire chip at once. be sure to hold the res pin low long enough for the clock to stabilize. 3. recovery by stby pin: when stby the pin goes low, the chip exits from the software standby mode to the hardware standby mode. 18.3.4 sample application of software standby mode in this example the chip enters the software standby mode on the falling edge of the nmi input and recovers from the software standby mode on the rising edge of nmi. figure 18-1 shows a timing chart of the transitions. the nonmaskable interrupt edge bit (nmieg) in the port 1 control register (p1cr) is originally cleared to 0, selecting the falling edge as the nmi trigger. after accepting an nmi interrupt in this condition, software changes the nmieg bit to 1, sets the ssby bit to 1, and executes the sleep instruction to enter the software standby mode. the chip recovers from the software standby mode on the next rising edge at the nmi pin. 324
18.3.5 application notes the i/o ports remain in their current states in the software standby mode. if a port is in the high output state, the output current is not reduced in the software standby mode. 18.4 hardware standby mode 18.4.1 transition to hardware standby mode regardless of its current state, the chip enters the hardware standby mode whenever the stby pin goes low. the hardware standby mode reduces power consumption drastically by halting the cpu, stopping all the functions of the on-chip supporting modules, and placing i/o ports in the high-impedance state. the registers of the on-chip supporting modules are reset to their initial values. only the on-chip ram is held unchanged, provided the minimum necessary voltage supply is maintained (see note 1). nmi nmeg ssby nmi interrupt handling nmieg = 1 ssby = 1 sleep instruction software standby mode (power-down state) clock start-up time clock settling time wdt overflow nmi interrupt handling oscillator wdt interval (t ) osc2 figure 18-1 nmi timing of software standby mode (application example) 325
notes: 1. the rame bit in the ram control register should be cleared to 0 before the stby pin goes low, to disable the on-chip ram during the hardware standby mode. 2. do not change the inputs at the mode pins (md2, md1, md0) during hardware standby mode. be particularly careful not to let all three mode inputs go low, since that would place the chip in prom mode, causing increased current dissipation. 18.4.2 recovery from hardware standby mode recovery from the hardware standby mode requires inputs at both the stby and res pins. when the stby pin goes high, the clock oscillator begins running. the res pin should be low at this time and should be held low long enough for the clock to stabilize. when the res pin changes from low to high, the reset sequence is executed and the chip returns to the program execution state. note: during standby mode, power must still be supplied to av cc , and the mode pins must be held at the selected mode. 18.4.3 timing sequence of hardware standby mode figure 18-2 shows the usual sequence for entering and leaving the hardware standby mode. first the res pin goes low, placing the chip in the reset state. then the stby pin goes low, placing the chip in the hardware standby mode and stopping the clock. in the recovery sequence first the stby pin goes high; then after the clock stabilizes, the res pin is returned to the high level. oscillator res stby clock settling time restart figure 18-2 hardware standby sequence 326
section 19 e clock interface 19.1 overview for interfacing to e clock based peripheral devices, the h8/534 and h8/536 can generate an e clock output. special instructions (movtpe, movfpe) perform data transfers synchronized with the e clock. the e clock is created by dividing the system clock (? by 8. the e clock is output at the p1 1 pin when the p1 1 ddr bit in the port 1 data direction register (p1ddr) is set to 1. when the cpu executes an instruction that synchronizes with the e clock, the address is output on the address bus as usual, but the data bus and the r/w, ds, rd, and wr signal lines do not become active until the falling edge of the e clock is detected. the length of the access cycle for an instruction synchronized with the e clock is accordingly variable. figures 19-1 and 19-2 show the timing in the cases of maximum and minimum synchronization delay. the wait state controller (wsc) does not insert any wait states (tw) during the execution of an instruction synchronized with the e clock. 327
as, t 1 t 2 t e t e t e t e t e t e t e t e t e t e t e t e t e t e t 3 last state e a to a 19 0 r/w ds (read access), rd ds (write access), wr d to d (read access) 7 0 d to d (write access) 7 0 figure 19-1 execution cycle of instruction synchronized with e clock in expanded modes (maximum synchronization delay) figure 19-1 execution cycle of instruction synchronized with e clock in expanded modes (maximum synchronization delay) 328
as, t 1 t 2 t e t e t e t e t e t e t e t 3 last state e a to a 19 0 r/w ds (read access), rd ds (write access), wr d to d (read access) 7 0 d to d (write access) 7 0 figure 19-2 execution cycle of instruction synchronized with e clock in expanded modes (minimum synchronization delay) 329
section 20 electrical specifications 20.1 absolute maximum ratings table 20-1 lists the absolute maximum ratings. table 20-1 absolute maximum ratings item symbol rating unit supply voltage v cc ?.3 to +7.0 v r-mask v pp ?.3 to +13.5 v s-mask ?.3 to +13.0 v input voltage (except port 8) v in ?.3 to v cc + 0.3 v (port 8) v in ?.3 to av cc + 0.3 v analog supply voltage av cc ?.3 to +7.0 v analog input voltage v an ?.3 to av cc + 0.3 v operating temperature t opr regular specifications: ?0 to +75 ?c wide-range specifications: ?0 to +85 ?c storage temperature t stg ?5 to +125 ?c note: permanent lsi damage may occur if maximum ratings are exceeded. normal operation should be under recommended operating conditions. 20.2 electrical characteristics 20.2.1 dc characteristics table 20-2 lists the dc characteristics. programming voltage 331 ?reliminary
table 20-2 dc characteristics ?preliminary for s-mask versions (5-v versions) conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10% * 1 , v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) t a = ?0 to +85?c (wide-range specifications) test item symbol min typ max unit conditions input high res, stby, v ih v cc ?0.7 v cc + 0.3 v voltage md 2 , md 1 , md 0 extal v cc 0.7 v cc + 0.3 v port 8 2.2 av cc + 0.3 v other input pins 2.2 v cc + 0.3 v (except port 7) input low res, stby, v il ?.3 0.5 v voltage md 2 , md 1 , md 0 other input pins ?.3 0.8 v (except port 7) schmitt port 7 v t 1.0 2.5 v trigger input v t + 2.0 3.5 v voltage v t + ?v t 0.4 v input res | i in | 10.0 a v in = 0.5 to leakage stby, nmi, 1.0 a v cc ?0.5 v current md 2 , md 1 , md 0 port 8 1.0 a v in = 0.5 to av cc ?0.5 v leakage cur- port 9, | i tsi | 1.0 a v in = 0.5 to rent in 3-state ports 7 to 1 v cc ?0.5 v (off state) input pull-up ports 6 r-mask ? p 50 200 a v in = 0 v mos current and 5 s-mask 50 300 a output high all output pins v oh v cc ?0.5 v i oh = ?00 a voltage 3.5 v i oh = ? ma output low all output pins v ol 0.4 v i ol = 1.6 ma voltage (except res) port 4 r-mask 1.0 v i ol = 8 ma 1.2 v i ol = 10 ma s-mask 1.0 v i ol = 10 ma res 0.4 v i ol = 2.6 ma note: * 1 avcc must be connected to a power supply line, even when the a/d converter is not used and even in standby mode. 332
table 20-2 dc characteristics ?preliminary for s-mask versions (5-v versions) (cont) test item symbol min typ max unit conditions input res h8/534 c in 60 pf v in = 0 v capacitance h8/536 100 pf f = 1 mhz nmi r-mask 30 pf t a = 25? s-mask 50 pf all input pins 15 pf except res, nmi current normal r-mask i cc 25 40 ma f = 6 mhz dissipation * 2 operation 30 50 ma f = 8 mhz 35 60 ma f = 10 mhz s-mask 40 60 ma f = 16 mhz sleep r-mask 12 25 ma f = 6 mhz mode 16 30 ma f = 8 mhz 20 35 ma f = 10 mhz s-mask 23 35 ma f = 16 mhz standby 0.01 5.0 a t a 50? 20.0 a t a > 50? analog supply during a/d r-mask ai cc 1.2 2.0 ma current conversion s-mask 1.5 3.0 ma while waiting 0.01 5.0 a ram standby voltage v ram 2.0 v note: * 2 current dissipation values assume that v ih min = v cc ?0.5 v, v il max = 0.5 v, all output pins are in the no-load state, and all mos input pull-ups are off. 333
table 20-3 dc characteristics (3-v s-mask versions) ?reliminary conditions: v cc = 3.0 to 5.5 v, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications), av cc = 3.0 to 5.5 v *1 test item symbol min typ max unit conditions input high res, stby, v ih v cc 0.85 v cc + 0.3 v voltage md 2 to md 0 extal v cc 0.7 v cc + 0.3 v port 8 2.2 av cc + 0.3 v other input pins 2.2 v cc + 0.3 v (except port 7) input low res, stby, v il ?.3 0.4 v voltage md 2 to md 0 , extal ?.3 0.8 v v cc 3 4.0 v ?.3 v cc 0.2 v v cc < 4.0 v port 7 v t v cc 0.2 v cc 0.5 v v t + v cc 0.4 v cc 0.7 v v t + ?v t v cc 0.07 v res |i in | 10.0 a stby, nmi, 1.0 a md 2 , md 1 , md 0 port 8 1.0 a v in = 0.5 to av cc ?0.5 v leakage port 9, ports 7 to 1 |i tsi | 1.0 a v in = 0.5 to current in v cc ?0.5 v 3-state (off-state) input pull-up ports 6 and 5 ? p 15 300 a v in = 0 v mos current output high all output pins v oh v cc ?0.4 v i oh = ?00 a v cc ?1.0 v i oh = ? ma note: * 1 av cc must be connected to a power supply line, even when the a/d converter is not used, and even in standby mode. schmitt trigger input voltages input leakage current output high voltage other input pins (except port 7) v in = 0.5 to v cc ?0.5 v 334
table 20-3 dc characteristics (3-v s-mask versions) (cont) ?reliminary item symbol min typ max unit output low all output pins v ol 0.4 v i ol = 1.6 ma voltage (except res) port 4 1.0 v i ol = 5 ma res 0.4 v i ol = 1.6 ma res h8/534 c in 60 pf h8/536 100 nmi 50 pf all input pins except 15 pf res and nmi current normal i cc 27 40 ma f = 10 mhz, dissipation * 2 operation v cc = 5 v 17 25 ma f = 10 mhz, v cc = 3 v sleep mode 15 25 ma f = 10 mhz, v cc = 5 v 10 15 ma f = 10 mhz, v cc = 3 v standby 0.01 5.0 a t a 50? 20.0 a 50? < t a ai cc 1.5 3.0 ma av cc = 5 v 0.5 1.0 ma av cc = 3 v while waiting 0.01 5.0 a ram standby voltage v ram 2.0 v note: * 2 current dissipation values assume that v ih min = v cc ?0.5 v and v il max = 0.5 v, all output pins are in the no-load state, and all mos input pull-ups are off. input capacitance analog supply current during a/d conversion v in = 0 v f = 1 mhz t a = 25? test conditions 335
table 20-4 dc characteristics (2.7-v s-mask versions) ?reliminary conditions: v cc = 2.7 to 5.5 v, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications), av cc = 2.7 to 5.5 v *1 item symbol min typ max unit input high res, stby, v ih v cc 0.85 v cc + 0.3 v voltage md 2 to md 0 extal v cc 0.7 v cc + 0.3 v port 8 2.2 av cc + 0.3 v other input pins 2.2 v cc + 0.3 v (except port 7) input low res, stby, v il ?.3 0.4 v voltage md 2 to md 0 , extal ?.3 0.8 v v cc 3 4.0 v ?.3 v cc 0.2 v v cc < 4.0 v port 7 v t v cc 0.2 v cc 0.5 v v t + v cc 0.4 v cc 0.7 v v t + ?v t v cc 0.07 v res |i in | 10.0 a stby, nmi, 1.0 a md 2 , md 1 , md 0 port 8 1.0 a v in = 0.5 to av cc ?0.5 v leakage port 9, ports 7 to 1 |i tsi | 1.0 a v in = 0.5 to current in v cc ?0.5 v 3-state (off-state) input pull-up ports 6 and 5 ? p 15 300 a v in = 0 v mos current all output pins v oh v cc ?0.4 v i oh = ?00 a v cc ?1.0 v i oh = ? ma note: * 1 av cc must be connected to a power supply line, even when the a/d converter is not used, and even in standby mode. schmitt trigger input voltages input leakage current output high voltage other input pins (except port 7) v in = 0.5 to v cc ?0.5 v test conditions 336
table 20-4 dc characteristics (2.7-v s-mask versions) (cont) ?reliminary item symbol min typ max unit output low all output pins v ol 0.4 v i ol = 1.6 ma voltage (except res) port 4 1.0 v i ol = 5 ma res 0.4 v i ol = 1.6 ma input res h8/534 c in 60 pf v in = 0 v h8/536 100 f = 1 mhz nmi 50 pf t a = 25? all input pins except 15 pf res and nmi current normal operation i cc 23 35 ma f = 8 mhz, dissipation * 2 v cc = 5 v 14 22 ma f = 8 mhz, v cc = 3 v sleep mode 12 22 ma f = 8 mhz, v cc = 5 v 8 14 ma f = 8 mhz, v cc = 3 v standby 0.01 5.0 a t a 50? 20.0 a 50? < t a ai cc 1.5 3.0 ma av cc = 5 v 0.5 1.0 ma av cc = 3 v while waiting 0.01 5.0 a ram standby voltage v ram 2.0 v note: * 2 current dissipation values assume that v ih min = v cc ?0.5 v and v il max = 0.5 v, all output pins are in the no-load state, and all mos input pull-ups are off. input capacitance analog supply current test conditions during a/d conversion 337
t able 20-5 allowable output curr ent v alues ?pr eliminar y for s-mask v ersions (5-v versions) conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications) t a = ?0 to +85?c (wide-range specifications) item symbol min typ max unit port 4 i ol 10 ma res 3.0 ma other output pins 2.0 ma port 4, total of 8 pins s i ol 40 ma total of all output pins 80 ma allowable output all output pins ? oh 2.0 ma high current (per pin) allowable output total of all output s ? oh 25 ma high current (total) pins table 20-6 allowable output current values (3-v s-mask versions) ?reliminary conditions: v cc = 3.0 to 5.5 v, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications), av cc = 3.0 to 5.5 v *1 item symbol min typ max unit port 4 i ol 10 ma res 3.0 ma other output pins 2.0 ma port 4, total of 8 pins s i ol 40 ma total of all output pins 80 ma allowable output all output pins ? oh 2.0 ma high current (per pin) allowable output total of all output pins s ? oh 25 ma high current (total) note: * 1 to avoid degrading the reliability of the chip, be careful not to exceed the output current sink values in table 20-5. in particular, when driving a darlington transistor pair or led directly, be sure to insert a current-limiting resistor in the output path. see figures 20-1 and 20-2. allowable output low current (per pin) allowable output low current (total) allowable output low current (per pin) allowable output low current (total) 338
table 20-7 allowable output current values (2.7-v s-mask versions) ?reliminary conditions: v cc = 2.7 to 5.5 v, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications), av cc = 2.7 to 5.5 v *1 item symbol min typ max unit port 4 i ol 10 ma res 3.0 ma other output pins 2.0 ma port 4, total of 8 pins s i ol 40 ma total of all output pins 80 ma allowable output all output pins ? oh 2.0 ma high current (per pin) allowable output total of all output pins s ? oh 25 ma high current (total) note: * 1 to avoid degrading the reliability of the chip, be careful not to exceed the output current sink values in table 20-5. in particular, when driving a darlington transistor pair or led directly, be sure to insert a current-limiting resistor in the output path. see figures 20-1 and 20-2. the s-mask versions (high-speed and low-voltage versions) are identical to the existing r-mask versions functionally and in their pin arrangement. due to the higher-speed design, however, there are differences in the fabrication process, which lead to some differences in electrical specifications, operating margin, noise margin, and other characteristics. these differences should be noted during board design, and when switching from an r-mask to an s-mask version. ?reliminary allowable output low current (per pin) allowable output low current (total) h8/534 h8/536 port 2 k darlington pair w h8/534 h8/536 port 4 600 led w v cc figure 20-1 example of circuit for driving a darlington transistor pair figure 20-2 example of circuit for driving an led 339
20.2.2 ac characteristics the ac characteristics of the h8/534 and h8/536 are listed in three tables. bus timing parameters are given in table 20-8, control signal timing parameters in table 20-9, and timing parameters of the on-chip supporting modules in table 20-10. table 20-8 (1) bus timing (r-mask versions) condition a (r-mask): v cc = 5.0 v 10%, ?= 0.5 to 10 mhz, v ss = 0 v t a = ?0 to +75?c (regular specifications) t a = ?0 to +85?c (wide-range specifications) condition a 6 mhz 8 mhz 10 mhz item symbol min max min max min max unit clock cycle time t cyc 166.7 2000 125 2000 100 2000 ns see figure 20-4 clock pulse width low t cl 65 45 35 ns clock pulse width high t ch 65 45 35 ns clock rise time t cr 15 15 15 ns clock fall time t cf 15 15 15 ns address delay time t ad 70 60 55 ns address hold time t ah 30 25 20 ns data strobe delay time 1 t dsd1 70 60 40 ns data strobe delay time 2 t dsd2 70 60 50 ns data strobe delay time 3 t dsd3 70 60 50 ns w rite data strobe pulse width t dsww 200 150 120 ns address setup time 1 t as1 25 20 15 ns address setup time 2 t as2 105 80 65 ns read data setup time t rds 60 50 40 ns read data hold time t rdh 0 0 0 ns read data access time t acc 280 190 160 ns w rite data delay time t wdd 70 65 65 ns w rite data setup time t wds 30 15 10 ns w rite data hold time t wdh 30 25 20 ns test conditions 340
table 20-8 (1) bus timing (r-mask versions) (cont) condition a 8 mhz 10 mhz 16 mhz item symbol min max min max min max unit w ait setup time t wts 40 40 40 ns see figure 20-5 w ait hold time t wth 10 10 10 ns bus request setup time t brqs 40 40 40 ns see figure 20-10 bus acknowledge delay time 1 t bacd1 70 60 55 ns bus acknowledge delay time 2 t bacd2 70 60 55 ns bus floating delay time t bzd t bacd1 t bacd1 t bacd1 ns e clock delay time t ed 20 15 15 ns see figure 20-1 1 e clock rise time t er 15 15 15 ns e clock fall time t ef 15 15 15 ns read data hold time t rdhe 0 0 0 ns see figure 20-6 (e clock sync) w rite data hold time t wdhe 50 40 30 ns (e clock sync) test conditions 341
table 20-8 (2) bus timing (s-mask versions) ?reliminary condition b (5-v s-mask): v cc = 5.0 v 10%, ?= 2.0 to 16 mhz, v ss = 0 v, t a = ?0 to +75?c (regular specifications), t a = ?0 to +85?c (wide-range specifications) condition c (3-v s-mask): v cc = 3.0 to 5.5 v, ?= 2.0 to 10 mhz, v ss = 0 v, t a = ?0 to +75?c (regular specifications) condition d (2.7-v s-mask): v cc = 2.7 to 5.5 v, ?= 2.0 to 8 mhz, v ss = 0 v, t a = ?0 to +75?c (regular specifications) condition d condition c condition b 8 mhz 10 mhz 16 mhz item symbol min max min max min max unit clock cycle time t cyc 125 500 100 500 62.5 500 ns clock pulse width low t cl 35 30 20 ns clock pulse width high t ch 35 30 20 ns clock rise time t cr 20 20 10 ns clock fall time t cf 20 20 10 ns address delay time t ad 60 55 30 ns address hold time t ah 20 10 5 ns data strobe delay time 1 t dsd1 60 40 30 ns data strobe delay time 2 t dsd2 60 50 30 ns data strobe delay time 3 t dsd3 60 50 30 ns write data strobe t dsww 150 120 70 ns pulse width address setup time 1 t as1 20 15 10 ns address setup time 2 t as2 80 65 30 ns read data setup time t rds 50 40 20 ns read data hold time t rdh 0 0 0 ns read data access time t acc 190 160 100 ns write data delay time t wdd 75 70 50 ns write data setup time t wds 15 10 10 ns write data hold time t wdh 25 20 10 ns wait setup time t wts 40 40 30 ns wait hold time t wth 10 10 10 ns bus request setup time t brqs 40 40 30 ns bus acknowledge t bacd1 60 55 30 ns delay time 1 test conditions see figure 20-4 see figure 20-5 see figure 20-10 342
table 20-8 (2) bus timing (s-mask versions) (cont) ?reliminary conditions d conditions c conditions b 8 mhz 10 mhz 16 mhz item symbol min max min max min max unit bus acknowledge t bacd2 60 55 30 ns see figure delay time 2 20-10 bus floating delay time t bzd t bacd1 t bacd1 t bacd1 ns e clock delay time t ed 20 20 10 ns e clock rise time t er 20 20 10 ns e clock fall time t ef 20 20 10 ns read data hold time t rdhe 0 0 0 ns see figure (e clock sync) 20-6 write data hold time t wdhe 40 30 10 ns (e clock sync) see figure 20-11 test condition 343
table 20-9 (1) control signal timing (r-mask versions) condition a (r-mask): v cc = 5.0 v 10%, ?= 0.5 to 10 mhz, v ss = 0 v, t a = ?0 to +75?c (regular specifications), t a = ?0 to +85?c (wide-range specifications) condition a 6 mhz 8 mhz 10 mhz item symbol min max min max min max unit res setup time t ress 200 200 200 ns res pulse width 1 * t resw1 6.0 6.0 6.0 t cyc res pulse width 2 * t resw2 520 520 520 t cyc res output delay time t resd 100 100 100 ns res output pulse width t resow 132 132 132 t cyc nmi setup time t nmis 150 150 150 ns nmi hold time t nmih 10 10 10 ns irq 0 setup time t irq0s 50 50 50 ns irq 1 setup time t irq1s 50 50 50 ns irq 1 hold time t irq1h 10 10 10 ns a/d trigger setup time t trgs 50 50 50 ns a/d trigger hold time t trgh 10 10 10 ns nmi pulse width (for t nmiw 200 200 200 ns recovery from software standby mode) crystal oscillator settling t osc1 20 20 20 ms see figure time (reset) 20-12 crystal oscillator settling t osc2 10 10 10 ms see figure time (software standby) 18-1 note : * t resw2 applies at power-on and when the rstoe bit in the reset control/status register (rstcsr) is set to 1. t resw1 applies when rstoe is cleared to 0. see figure 20-7 see figure 20-8 see figure 20-9 see figure 20-22 t est condition 344
table 20-9 (2) control signal timing (s-mask versions) ?reliminary condition b (5-v s-mask): v cc = 5.0 v 10%, ?= 2.0 to 16 mhz, v ss = 0 v, t a = ?0 to +75?c (regular specifications), t a = ?0 to +85?c (wide-range specifications) condition c (3-v s-mask): v cc = 3.0 to 5.5 v, ?= 2.0 to 10 mhz, v ss = 0 v, t a = ?0 to +75?c (regular specifications) condition d (2.7-v s-mask): v cc = 2.7 to 5.5 v, ?= 2.0 to 8 mhz, v ss = 0 v, t a = ?0 to +75?c (regular specifications) condition d condition c condition b 8 mhz 10 mhz 16 mhz item symbol min max min max min max unit res setup time t ress 200 200 200 ns res pulse width 1 * t resw1 6.0 6.0 6.0 t cyc res pulse width 2 * t resw2 520 520 520 t cyc res output delay time t resd 100 100 100 ns res output pulse width t resow 132 132 132 t cyc nmi setup time t nmis 200 200 150 ns nmi hold time t nmih 10 10 10 ns irq 0 setup time t irq0s 50 50 50 ns irq 1 setup time t irq1s 50 50 50 ns irq 1 hold time t irq1h 10 10 10 ns a/d trigger setup time t trgs 50 50 50 ns a/d trigger hold time t trgh 10 10 10 ns nmi pulse width t nmiw 200 200 200 ns (for recovery from software standby mode) crystal oscillator t osc1 20 20 20 ms see figure settling time (reset) 20-12 crystal oscillator t osc2 10 10 10 ms see figure settling time 18-1 (software standby) note: * t resw2 applies at power-on and when the rst oe bit in the reset contol/status register (rstcsr) is set to 1. t resw1 applies when rst oe is cleared to 0. see figure 20-7 see figure 20-8 see figure 20-9 see figure 20-22 t est conditions 345
t able 20-10 t iming conditions of on-chip ?preliminar y for s-mask v ersions suppor ting modules condition a (r-mask): v cc = 5.0 v 10%, ?= 0.5 to 10 mhz, v ss = 0 v, t a = ?0 to +75?c(regular specifications), t a = ?0 to +85?c (wide-range specifications) condition b (5-v s-mask): v cc = 5.0 v 10%, ?= 2.0 to 16 mhz, v ss = 0 v, t a = ?0 to +75?c (regular specifications), t a = ?0 to +85?c (wide-range specifications) condition c (3-v s-mask): v cc = 3.0 to 5.5 v, ?= 2.0 to 10 mhz, v ss = 0 v, t a = ?0 to +75?c (regular specifications) condition d (2.7-v s-mask): v cc = 2.7 to 5.5 v, ?= 2.0 to 8 mhz, v ss = 0 v, t a = ?0 to +75?c (regular specifications) condition a condition d condition c condition b 6 mhz 8 mhz 10 mhz 16 mhz item symbol min max min max min max min max unit frt timer output t ftod 100 100 100 100 ns see figure delay time 20-14 timer input t ftis 50 50 50 50 ns setup time timer clock t ftcs 50 50 50 50 ns see figure input setup time 20-15 timer clock t ftcwl , 1.5 1.5 1.5 1.5 tcyc pulse width t ftcwh tmr timer output t tmod 100 100 100 100 ns see figure delay time 20-16 timer clock t tmcs 50 50 50 50 ns see figure input setup time 20-17 timer clock t tmcwl , 1.5 1.5 1.5 1.5 tcyc pulse width t tmcwh timer reset t tmrs 50 50 50 50 ns see figure input setup time 20-18 pwm timer output t pwod 100 100 100 100 ns see figure delay time 20-19 t est conditions 346
t able 20-10 t iming conditions of on-chip ?pr eliminar y for s-mask v ersions suppor ting modules (cont) condition a condition d condition c condition b 6 mhz 8 mhz 10 mhz 16 mhz item symbol min max min max min max min max unit sci input (async) t scyc 2 2 2 2 t cyc (sync) 4 4 4 4 t cyc input t sckw 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 t scyc pulse width transmit (sync) t txd 100 100 100 100 ns see figure data delay 20-21 receive (sync) t rxs 100 100 100 100 ns data setup time receive (sync) t rxh 100 100 100 100 ns data hold time port output data t pwd 100 100 100 100 ns see figure delay time 20-13 input data setup time t prs 50 50 50 50 ns input data hold time t prh 50 50 50 50 ns ? measurement conditions for ac characteristics h8/534 (h8/536) output pin 5 v c r h c r r input/output timing reference levels low: high: = 90 pf: p1, p2, p3, p4, p5, p6 = 30 pf: p7, p9 = 2.4 k = 12 k 0.8 v 2.0 v l h r l w w figure 20-3 output load circuit input clock cycle test conditions see figure 20-20 347
t ah , t dsww , t as1 , t as2 , and t acc depend on t cyc as shown below. ?reliminary (1) v cc = 5.0 v 10% (s-mask) t ah = 0.5 t cyc ?26 (ns) t as2 = t cyc ?32 (ns) t dsww = 1.5 t cyc ?24 (ns) t acc = 2.5 t cyc ?56 (ns) t as1 = 0.5 t cyc ?21 (ns) (2) v cc = 3.0 v (s-mask) t ah = 0.5 t cyc ?40 (ns) t as2 = t cyc ?35 (ns) t dsww = 1.5 t cyc ?30 (ns) t acc = 2.5 t cyc ?90 (ns) t as1 = 0.5 t cyc ?35 (ns) (3) v cc = 2.7 v (s-mask) t ah = 0.5 t cyc ?42 (ns) t as2 = t cyc ?45 (ns) t dsww = 1.5 t cyc ?37 (ns) t acc = 2.5 t cyc ?122 (ns) t as1 = 0.5 t cyc ?42 (ns) 348
20.2.3 a/d converter characteristics tables 20-11 and 20-12 list the characteristics of the on-chip a/d converter. tables 20-11 a/d conver ter characteristics ?preliminar y for s-mask v ersions (5-v versions) conditions: v cc = 5.0v 10%, av cc = 5.0v 10%, v ss = av ss = 0v, t a = ?0 to +75?c (regular specifications) t a = ?0 to +85?c (wide-range specifications) r-mask s-mask 6 mhz 8 mhz 10 mhz 16 mhz item min t yp max min t yp max min t yp max min t yp max unit resolution 10 10 10 10 10 10 10 10 10 10 10 10 bits conversion time 23.0 17.25 13.8 8.625 s analog input 20 20 20 20 pf capacitance allowable signal- 10 10 10 5 k source impedance nonlinearity error 2.0 2.0 2.0 2.0 lsb offset error 2.0 2.0 2.0 2.0 lsb full-scale error 2.0 2.0 2.0 2.0 lsb quantizing error 0.5 0.5 0.5 0.5 lsb absolute accuracy 2.5 2.5 2.5 2.5 lsb 349
table 20-12 a/d converter characteristics ?reliminary condition c (3-v s-mask): v cc = 3.0 to 5.5 v, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications), av cc = 3.0 to 5.5 v condition d (2.7-v s-mask): v cc = 2.7 to 5.5 v, v ss = av ss = 0 v, t a = ?0 to +75?c (regular specifications), av cc = 2.7 to 5.5 v condition d * 1 condition c * 2 8 mhz 10 mhz item min t yp max min t yp max unit resolution 10 10 10 10 10 10 bits conversion time 17.25 13.8 s analog input capacitance 20 20 pf allowable signal-source impedance 5 5 k w nonlinearity error 3.5 3.5 lsb offset error 3.5 3.5 lsb full-scale error 3.5 3.5 lsb quantizing error 0.5 0.5 lsb absolute accuracy 4.0 4.0 lsb notes : maximum operating frequency of a/d converter: * 1 av cc = 2.7 to 3.0 v: 8 mhz (conversion time: 17.25 s) * 2 av cc = 3.0 to 4.5 v: 10 mhz (conversion time: 13.8 s) 20.3 mcu operational timing this section provides the following timing charts: 20.3.1 bus timing figures 20-4 to 20-6 20.3.2 control signal timing figures 20-7 to 20-10 20.3.3 clock timing figures 20-11 and 20-12 20.3.4 i/o port timing figure 20-13 20.3.5 16-bit free-running timer timing figures 20-14 and 20-15 20.3.6 8-bit timer timing figures 20-16 to 20-18 20.3.7 pulse width modulation timer timing figure 20-19 20.3.8 serial communication interfacetiming figure 20-20 and 20-21 350
20.3.1 bus timing 1. basic bus cycle (without wait states) in expanded modes as, a to a 19 0 r/w ds (read), rd ds (write), d to d (read) 7 0 d to d (write) 7 0 wr t ch t cyc t 1 t 2 t 3 t cl t ad t cf t cr t dsd1 t as1 t acc t dsd2 t as2 t wds t wdd t dsd3 t dsww t rds t rdh t wdh t ah t ah t dsd3 figure 20-4 basic bus cycle (without wait states) in expanded modes 351
2. basic bus cycle (with 1 wait state) in expanded modes t 1 t 2 t w t 3 a to a 19 0 r/w ds (read), rd ds (write), d to d (read) 7 0 d to d (write) 7 0 rd wait t wts t wth t wts t wth figure 20-5 basic bus cycle (with 1 wait state) in expanded modes 352
3. bus cycle synchronized with e clock a to a 19 0 r/w ds (read), rd d to d (read) 7 0 d to d (write) 7 0 ds (write), wr as, e t rds t wdhe t ah t rdhe t ed t dsd3 t ah t dsd3 figure 20-6 bus cycle synchronized with e clock 353
20.3.2 control signal timing 1. reset input timing 2. reset output timing 3. nmi pulse width res t resw1 t ress t ress t resw2 , res t resow t resd t resd irq 0 5 nmi t irq1s t irq0s t irq1h t nmih t nmis irq to irq 1 figure 20-7 reset input timing figure 20-8 reset output timing figure 20-9 interrupt input timing 354
4. bus release state timing 20.3.3 clock timing 1. e clock timing breq (input) fig. 20-10 back (output) a to a , r/w, ds, rd, wr, as 19 0 t brqs t bacd1 t bzd t brqs t bacd2 t ad fig. 20-11 e t ef t ed t ed t er figure 20-10 bus release state timing figure 20-11 e clock timing 355
2. clock oscillator stabilization timing fig. 20-12 stby res v cc t osc1 t osc1 figure 20-12 clock oscillator stabilization timing 356
20.3.4 i/o port timing fig. 20-13 t prs t prh t pwd t 1 t 2 t 3 port 1 to (input) port 9 port 1 to (output) port 9 except p1 , p1 , and p8 to p8 1 0 7 0 port read/write cycle * * figure 20-13 i/o port input/output timing 357
20.3.5 16-bit free-running timer timing 1. free-running timer input/output timing 2. external clock input timing for free-running timers fig. 20-14 t ftod free-running timer counter ftoa , ftob , 1 1 ftoa , ftob , 2 2 ftoa , ftob 3 3 fti , fti , fti 1 3 2 compare-match t ftis t ftcs t ftcwl t ftcwh ftci , 1 ftci , 2 ftci 3 figure 20-14 free-running timer input/output timing figure 20-15 external clock input timing for free-running timers 358
20.3.6 8-bit timer timing 1. 8-bit timer output timing 2. 8-bit timer clock input timing 3. 8-bit timer reset input timing fig. 20-16 t tmod timer counter tmo compare-match fig. 20-17 tmci t tmcs t tmcs t tmcwl t tmcwh fig. 20-18 t tmrs n tmri timer counter h'00 figure 20-16 8-bit timer output timing figure 20-17 8-bit timer clock input timing figure 20-18 8-bit timer reset input timing 359
20.3.7 pulse width modulation timer timing 20.3.8 serial communication interface timing pw , pw , 1 t pwod compare-match timer counter 2 pw 3 t sckw t scyc t scyc t rxd t rxs t rxh serial clock transmit data receive data figure 20-19 pwm timer output timing figure 20-20 sci input clock timing figure 20-21 sci input/output timing (synchronous mode) 360
20.3.9 a/d trigger signal input timing figure 20-22 a/d trigger signal input timing adtrg t trgh t trgs 361
appendix a instructions a.1 instruction set operation notation rd general register (destination operand) fp frame pointer rs general register (source operand) #imm immediate data rn general register disp displacement (ead) destination operand + add (eas) source operand subtract ccr condition code register multiply n n (negative) flag in ccr ? divide z z (zero) flag in ccr logical and v v (overflow) flag in ccr logical or c c (carry) flag in ccr ? logical exclusive or cr control register ? move pc program counter ? swap cp code page register logical not sp stack pointer condition code notation changed after instruction execution 0 cleared to 0 1 set to 1 value before operation is retained ? changed depending on condition 363
size ccr bit mnemonic operation b/w n z v c data mov: g (eas) ?? rd b/w 0 transfer rs ?? (ead) #imm ?? (ead) mov: e #imm ?? rd (short format) b 0 mov: f @ (d: 8, fp) ?? rd b/w 0 rs ?? @ (d: 8, fp)(short format) mov: i #imm ?? rd (short format) w 0 mov: l (@aa: 8) ?? rd (short format) b/w 0 mov: s rs ?? (@aa: 8) (short format) b/w 0 ldm @ sp + ?? rn (register list) w stm rn (register list) ?? @ ?sp w xch rs ??? rd w swap rd (upper byte) ??? rd (lower byte) b 0 movtpe rs ?? (ead) synchronized with e clock b movfpe (eas) ?? rd synchronized with e clock b arith- add: g rd + (eas) ?? rd b/w metic add: q (ead) + #imm ?? (ead) b/w opera- (#imm = 1, 2) (short format) tions adds rd + (eas) ?? rd b/w (rd is always word size) addx rd + (eas) + c ?? rd b/w dadd (rd) 10 + (rs) 10 + c ?? (rd) 10 b sub rd ?(eas) ?? rd b/w subs rd ?(eas) ?? rd b/w subx rd ?(eas) ?c ?? rd b/w dsub (rd) 10 ?(rs) 10 ?c ?? (rd) 10 b mulxu rd (eas) ?? rd 8 8 b/w 0 0 (unsigned) 16 16 divxu rd ? (eas) ?? rd 16 ? 8 b/w 0 (unsigned) 32 ? 16 cmp: g rd ?(eas), set ccr b/w (ead) ?#imm, set ccr cmp: e rd ?#imm, set ccr (short format) b cmp: i rd ?#imm, set ccr (short format) w 364
size ccr bit mnemonic operation b/w n z v c arith- exts (< bit 7 > of < rd >) b 0 0 metic ?? (< bit 15 to 8 > of < rd >) opera- extu 0 ?? ( of < rd >) b 0 0 0 tions tst (ead) ?0, set ccr b/w 0 0 neg 0 ?(ead) ?? (ead) b/w 0 clr 0 ?? (ead) b/w 0 1 0 0 tas (ead) ?0, set ccr b 0 0 (1) 2 ?? (< bit 7 > of < ead >) shift shal b/w opera- tions shar b/w 0 shll b/w 0 shlr b/w 0 0 rotl b/w 0 rotr b/w 0 rotxl b/w 0 rotxr b/w 0 logic and rd (eas) ?? rd b/w 0 opera- or rd (eas) ?? rd b/w 0 tions xor rd ? (eas) ?? rd b/w 0 not (ead) ?? (ead) b/w 0 bit bset (< bit number > of < ead >) ?? z b/w manipu- 1 ?? (< bit number > of < ead >) lations bclr (< bit number > of < ead >) ?? z b/w 0 ?? (< bit number > of < ead >) btst (< bit number > of < ead >) ?? z b/w bnot (< bit number > of < ead >) ?? z b/w ?? (< bit number > of < ead >) msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb msb lsb c c c c 0 c c 0 0 c c 365
size ccr bit mnemonic operation b/w n z v c branch- bcc if condition is true then ing pc + disp ?? pc instruc- else next; tions jmp effective address ?? pc pjmp effective address ?? cp, pc bsr pc ?? @ ?sp pc + disp ?? pc jsr pc ?? @ ?sp effective address ?? pc pjsr pc ?? @ ?sp cp ?? @ ?sp effective address ?? cp, pc rts @ sp + ?? pc prts @ sp + ?? cp @ sp + ?? pc rtd @ sp + ?? pc sp + #imm ?? sp prtd @ sp + ?? cp @ sp + ?? pc sp + #imm ?? sp scb if condition is true then next; scb/f else rn ?1 ?? rn; scb/ne if rn = ? then next; scb/eq else pc + disp ?? pc; mnemonic description condition bra (bt) always (true) true brn (bf) never (false) false bhi high c z = 0 bls low or same c z = 1 bcc (bhs) carry clear (high or same) c = 0 bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n ? v = 0 blt less than n ? v = 1 bgt greater than z (n ? v) = 0 ble less or equal z (n ? v) = 1 mnemonic description condition scb/f false scb/ne not equal z = 0 scb/eq equal z = 1 366
size ccr bit mnemonic operation b/w n z v c system trapa pc ?? @ ?sp control (if max mode cp ?? @ ?sp) sr ?? @ ?sp (if max mode < vector > ?? cp) < vector > ?? pc trap/vs if v bit = ??then trap else next; rte @ sp + ?? sr (if max mode @ sp + ?? cp) @ sp + ?? pc link fp (r6) ?? @ ?sp sp ?? fp (r6) sp + #imm ?? sp unlk fp (r6) ?? sp @sp + ?? fp sleep normal running mode ?? power-down state ldc (eas) ?? cr b/w * stc cr ?? (ead) b/w * andc cr #imm ?? cr b/w * orc cr #imm ?? cr b/w * xorc cr ? #imm ?? cr b/w * nop pc + 1 ?? pc * depends on the cr. 367
a.2 instruction codes table a-1(a) to (d) shows the machine-language coding of each instruction. ? how to read table a-1 (a) to (d) the general operand format consists of an effective address (ea) field and operation-code (op) field specified in the following order. ea field op field 1 2 3 4 5 6 bytes 2, 3, 5, 6 are not present in all instructions. 368
instruction operation code (op) instruction mov:g.b , r s d mov:g.w , r s d mov:g.b r , s d mov:g.w r , s d 2 3 4 2 2 3 4 4 10010r r r 2 3 4 2 2 3 4 2 2 3 4 2 2 3 4 2 2 3 4 2 2 3 4 3 4 3 s s s 10010r r r s s s 10000r r r d d d 10000r r r d d d 4 5 6 byte length of instruction shading indicates addressing modes not available for this instruction. some instructions have a special format in which the operation code comes first. the following notation is used in the tables. sz: byte: word: operand size (byte or word) sz = 0 sz = 1 address- ing mode rn @rn @(d:8, rn) @(d:16, rn) @ern @rn+ @aa:8 @aa:16 #xx:8 #xx:16 1 0 1 0 sz r r r 1 1 0 1 sz r r r 1 1 1 0 sz r r r 1 1 1 1 sz r r r 1 0 1 1 sz r r r 1 1 0 0 sz r r r 0 0 0 0 sz 1 0 1 0 0 0 1 sz 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 2 3 operation code (ea) disp disp (h) address address (h) data data (h) disp (l) address (l) data (l) 369
? rrr : general register number field rrr sz = 0 (byte) sz = 1 (word) 15 8 7 0 15 0 000 not used r0 r0 001 not used r1 r1 010 not used r2 r2 011 not used r3 r3 100 not used r4 r4 101 not used r5 r5 110 not used r6 r6 111 not used r7 r7 ? ccc : control register number field ccc sz = 0 (byte) sz = 1 (word) 000 (not allowed * ) 001 (not allowed) 010 (not allowed) (not allowed) 011 br (not allowed) 100 ep (not allowed) 101 dp (not allowed) 110 (not allowed) (not allowed) 111 tp (not allowed) * ?ot allowed?means that this combination of bits must not be specified. specifying a disallowed combination may cause abnormal results. 370 15 0 sr 7 0 ccr
? register list: a byte in which bits indicate general registers as follows ? #vec: four bits designating a vector number from 0 to 15. the vector numbers correspond to addresses of entries in the exception vector table as follows: vector address vector address #vec minimum mode maximum mode #vec minimum mode maximum mode 0 h'0020 ?h'0021 h'0040 ?h'0043 8 h'0030 ?h'0031 h'0060 ?h'0063 1 h'0022 ?h'0023 h'0044 ?h'0047 9 h'0032 ?h'0033 h'0064 ?h'0067 2 h'0024 ?h'0025 h'0048 ?h'004b 10 h'0034 ?h'0035 h'0068 ?h'006b 3 h'0026 ?h'0027 h'004c ?h'004f 11 h'0036 ?h'0037 h'006c ?h'006f 4 h'0028 ?h'0029 h'0050 ?h'0053 12 h'0038 ?h'0039 h'0070 ?h'0073 5 h'002a ?h'002b h'0054 ?h'0057 13 h'003a ?h'003b h'0074 ?h'0077 6 h'002c ?h'002d h'0058 ?h'005b 14 h'003c ?h'003d h'0078 ?h'007b 7 h'002e ?h'002f h'005c ?h'005f 15 h'003e ?h'003f h'007c ?h'007f ? examples of machine-language coding example 1: add:g.b @r0, r1 ea field op field notes table a-1 (a) 1101szrrr 00100r d r d r d machine code for add:g.b @rs, rd machine code 11010000 00100 0 0 1 sz = 0 (byte) h'd021 rs = r0, rd = r1 example 2: add:g.w @h'11:8, r1 ea field op field notes table a-1 (a) 0000sz101 00010001 00100r d r d r d machine code for add:g.w @aa:8, rd machine code 0000 1 101 00010001 00100 0 0 1 sz = 1 (word) h'0d1121 aa = h'11, rd = r1 bit 7 6 5 4 3 2 1 0 r7 r6 r5 r4 r3 r2 r1 r0 371
instruction operation code (op) data transfer instruction mov:g.b , r s d mov:g.w , r s d mov:g.b r , s d mov:g.w r , s d 2 3 4 2 2 3 4 4 10010 2 3 4 2 2 3 4 2 2 3 4 2 2 3 4 2 2 3 4 2 2 3 4 3 4 10010 10000 10000 d 4 5 6 note: short format instruction address- ing mode rn @rn @(d:8, rn) @(d:16, rn) @ern @rn+ @aa:8 @aa:16 #xx:8 #xx:16 1 0 1 0 sz r r r 1 1 0 1 sz r r r 1 1 1 0 sz r r r 1 1 1 1 sz r r r 1 0 1 1 sz r r r 1 1 0 0 sz r r r 0 0 0 0 sz 1 0 1 0 0 0 1 sz 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 2 3 operation code (ea) disp disp (h) address address (h) data data (h) disp (l) address (l) data (l) mov:g.b #xx:8, d 3 4 5 3 3 4 5 00000110 r d r d r d r d r d r s r s r s r s r s r s r data mov:g.w #xx:8, d 3 4 5 3 3 4 5 00000110 data mov:g.w #xx:16, d 4 5 6 4 4 5 6 00000111 data (h) data (l) ldm.w @sp+, 2 00000010 register list stm.w ,@esp 2 00000010 register list xch.w r ,r s d 2 10010 d r d r d r swap.b r d 2 00010000 movtpe.b r , s d 3 4 5 3 3 4 5 00000000 10010 s r s r s r movtpe.b , r s d 3 4 5 3 3 4 5 00000000 10010 d r d r d r arithmetic operation instruction add:g.b , r s d 2 2 3 4 2 2 3 4 3 00100 d r d r d r add:g.w , r d 2 2 3 4 2 2 3 4 4 00100 d r d r d r s add:q.b #1, d 2 2 3 4 2 2 3 4 00001000 * add:q.w #1, d 2 2 3 4 2 2 3 4 00001000 * add:q.b #2, d 2 2 3 4 2 2 3 4 00001001 * add:q.w #2, d 2 2 3 4 2 2 3 4 00001001 * add:q.b #-1, d 2 2 3 4 2 2 3 4 00001100 * add:q.w #-1, d 2 2 3 4 2 2 3 4 00001100 * add:q.b #-2, d 2 2 3 4 2 2 3 4 00001101 * add:q.w #-2, d 2 2 3 4 2 2 3 4 00001101 * adds.b , r d 2 2 3 4 2 2 3 4 3 00101 d r d r d r s adds.w , r d 2 2 3 4 2 2 3 4 4 00101 d r d r d r s addx.b , r d 2 2 3 4 2 2 3 4 3 10100 d r d r d r s addx.w , r d 2 2 3 4 2 2 3 4 4 10100 d r d r d r s * table a-1 (a) machine language coding [general format] 372
instruction operation code (op) dadd.b r ,r s d sub.b , r s d sub.w , r s d subs.b , r s d 2 3 4 2 2 3 4 00111 2 3 4 2 2 3 4 2 2 3 4 2 2 3 4 4 3 00110 00110 00000000 4 5 6 address- ing mode rn @rn @(d:8, rn) @(d:16, rn) @ern @rn+ @aa:8 @aa:16 #xx:8 #xx:16 1 0 1 0 sz r r r 1 1 0 1 sz r r r 1 1 1 0 sz r r r 1 1 1 1 sz r r r 1 0 1 1 sz r r r 1 1 0 0 sz r r r 0 0 0 0 sz 1 0 1 0 0 0 1 sz 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 2 3 operation code (ea) disp disp (h) address address (h) data data (h) disp (l) address (l) data (l) subs.w ,r d 2 3 4 2 2 3 4 00111 d r d r d r d r d r d r d r d r d r subx.b , r d 2 3 4 2 2 3 4 10110 data subx.w , r d 2 3 4 2 2 3 4 10110 data (h) data (l) dsub.b r , r 00000000 mulxu.b , r s 2 10101 mulxu.x , r s d 2 10101 d r d r d r divxu.b , r d 2 10111 divxu.w , r s d 2 3 4 2 2 3 4 10111 cmp:g.b , r s d 3 4 5 3 3 4 5 01110 10100 d r d r d r arithmetic operation instruction cmp:g.w , r s d 2 2 3 4 2 2 3 4 3 01110 d r d r d r cmp:g.b #xx, d 3 4 5 3 3 4 5 00000100 cmp:g.w #xx, d 4 5 6 4 4 5 6 00000101 exts.b r d 2 00010001 extu.b r d 2 00010010 tst.b d 2 2 3 4 2 2 3 4 00010110 tst.w d 2 2 3 4 2 2 3 4 00010110 neg.b d 2 2 3 4 2 2 3 4 00010100 neg.w d 2 2 3 4 2 2 3 4 00010100 clr.b d 2 2 3 4 2 2 3 4 00010011 clr.w d 2 2 3 4 2 2 3 4 00010011 tas.b d 2 2 3 4 2 2 3 4 00010111 s s s d s d s 4 3 4 3 4 2 2 2 3 2 2 3 4 4 2 3 2 2 3 4 4 2 3 2 3 4 4 2 3 2 4 2 3 2 4 2 3 2 10110 d r d r d r d r d r d r d r d r d r d r d r d r d r d r d r d r d r d r d r d r d r d r d r d r table a-1 (a) machine language coding [general format] (cont) 373
instruction operation code (op) shal.b d shal.w d shar.b d shar.w d 2 3 4 2 2 3 4 00011001 2 3 4 2 2 3 4 2 2 3 4 2 2 3 4 00011001 00011000 00011000 4 5 6 address- ing mode rn @rn @(d:8, rn) @(d:16, rn) @ern @rn+ @aa:8 @aa:16 #xx:8 #xx:16 1 0 1 0 sz r r r 1 1 0 1 sz r r r 1 1 1 0 sz r r r 1 1 1 1 sz r r r 1 0 1 1 sz r r r 1 1 0 0 sz r r r 0 0 0 0 sz 1 0 1 0 0 0 1 sz 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 2 3 operation code (ea) disp disp (h) address address (h) data data (h) disp (l) address (l) data (l) shll.b d 2 3 4 2 2 3 4 00011010 shll.w d 2 3 4 2 2 3 4 00011010 shlr.b d 2 3 4 2 2 3 4 00011011 shlr.w 00011011 rotl.b 2 00011100 rotl.w d 2 00011100 d r d r d r rotr.b d 2 00011101 rotr.w d 2 3 4 2 2 3 4 00011101 rotxl.b d 2 3 4 2 2 3 4 00011110 shift instruction rotxl.w d 2 2 3 4 2 2 3 4 3 00011110 d r d r d r rotxr.b d 2 3 4 2 2 3 4 00011111 rotxr.w d 2 3 4 2 2 3 4 00011111 and.b , r d 2 01010 and.w , r d 2 01010 or.b.b , r d 2 2 3 4 2 2 3 4 01000 or.b.w , r d 2 2 3 4 2 2 3 4 01000 xor.b , r d 2 2 3 4 2 2 3 4 01100 xor.w , r d 2 2 3 4 2 2 3 4 01100 not.b d 2 2 3 4 2 2 3 4 00010101 not.w d 2 2 3 4 2 2 3 4 00010101 d d 4 3 4 3 4 2 2 2 3 2 2 3 4 4 2 3 2 2 3 4 4 2 3 2 3 4 4 2 2 2 2 2 2 2 d r d r d r d r d r d r d r d r d r d r d r d r logic operation instruction s s s s s s 2 3 4 2 2 3 4 2 3 4 2 2 3 4 2 2 2 2 3 2 3 4 4 2 2 3 4 2 2 3 4 table a-1 (a) machine language coding [general format] (cont) 374
instruction operation code (op) bset.b #xx, d bset.w #xx, d bset.b r , d bset.w r , s 2 3 4 2 2 3 4 01001 2 3 4 2 2 3 4 2 2 3 4 2 2 3 4 01001 1100 1100 4 5 6 address- ing mode rn @rn @(d:8, rn) @(d:16, rn) @ern @rn+ @aa:8 @aa:16 #xx:8 #xx:16 1 0 1 0 sz r r r 1 1 0 1 sz r r r 1 1 1 0 sz r r r 1 1 1 1 sz r r r 1 0 1 1 sz r r r 1 1 0 0 sz r r r 0 0 0 0 sz 1 0 1 0 0 0 1 sz 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 2 3 operation code (ea) disp disp (h) address address (h) data data (h) disp (l) address (l) data (l) bclr.b #xx, d 2 3 4 2 2 3 4 1101 bclr.w #xx, d 2 3 4 2 2 3 4 1101 bclr.b r , s 2 3 4 2 2 3 4 01011 bclr.w r , 01011 btst.b #xx, 2 1111 btst.w #xx, d 2 1111 btst.b r , s 2 01111 btst.w r , s 2 3 4 2 2 3 4 01111 bnot.b #xx, d 2 3 4 2 2 3 4 1110 bit manipulate instruction bnot.w #xx, d 2 2 3 4 2 2 3 4 1110 bnot.b r , s 2 3 4 2 2 3 4 01101 bnot.w r , s 2 3 4 2 2 3 4 01101 ldc.b , cr 2 10001ccc ldc.w , cr 2 10001ccc stc.b cr, d 2 2 3 4 2 2 3 4 10011ccc stc.w cr, d 2 2 3 4 2 2 3 4 10011ccc andc.b #xx:8, cr 01011ccc andc.w #xx:16, cr 01011ccc orc.b #xx:8, cr 01001ccc orc.w #xx:16, cr 01001ccc d 3 4 3 4 2 2 2 3 2 2 3 4 4 2 3 2 2 3 4 4 2 3 2 3 4 4 2 2 2 2 2 2 2 system control instruction s s 2 3 4 2 2 3 4 2 3 4 2 2 3 4 2 2 2 2 3 2 3 4 4 2 2 3 4 2 2 3 4 s d d d s d d d d xorc.b #xx:8, cr xorc.w #xx:16, cr 3 4 3 4 (data) (data) s r s r s r s r s r s r (data) (data) s r s r s r s r s r s r (data) (data) s r s r s r s r s r s r (data) (data) s r s r s r s r s r s r 01101ccc 01101ccc table a-1 (a) machine language coding [general format] (cont) 375
table a-1 (b) machine language coding [special format: short format] operation code 1 2 3 4 mov:e,b #xx:8,rd 2 01010r d r d r d data mov:i.w #xx:16,rd 3 01011r d r d r d data (h) data (l) mov:l.b @aa:8,rd 2 01100r d r d r d address (l) mov:l.w @aa:8,rd 2 01101r d r d r d address (l) mov:s.b rs,@aa:8 2 01110r s r s r s address (l) mov:s.w rs,@aa:8 2 01111r s r s r s address (l) mov:f.b @(d:8,r6),rd 2 10000r d r d r d disp mov:f.w @(d:8,r6),rd 2 10001r d r d r d disp mov:f.b rs @(d:8,r6) 2 10010r s r s r s disp mov:f.w rs,@(d:8,r6) 2 10011r s r s r s disp cmp:e #xx:8,rd 2 01000r d r d r d data cmp:i #xx:16,rd 3 01001r d r d r d data (h) data (l) instruction bytes 376
table a-1 (c) machine language coding [special format: branch instruction] operation code 1 2 3 4 bcc d:8 bra (bt) 2 00100000 disp brn (bf) 00100001 disp bhi 00100010 disp bls 00100011 disp bcc (bhs) 00100100 disp bcs (blo) 00100101 disp bne 00100110 disp beq 00100111 disp bvc 00101000 disp bvs 00101001 disp bpl 00101010 disp bmi 00101011 disp bge 00101100 disp blt 00101101 disp bgt 00101110 disp ble 00101111 disp bcc d:16 bra (bt) 3 00110000 disp (h) disp (l) brn (bf) 00110001 disp (h) disp (l) bhi 00110010 disp (h) disp (l) bls 00110011 disp (h) disp (l) bcc (bhs) 00110100 disp (h) disp (l) bcs (blo) 00110101 disp (h) disp (l) bne 00110110 disp (h) disp (l) beq 00110111 disp (h) disp (l) bvc 00111000 disp (h) disp (l) bvs 00111001 disp (h) disp (l) bpl 00111010 disp (h) disp (l) bmi 00111011 disp (h) disp (l) bge 00111100 disp (h) disp (l) blt 00111101 disp (h) disp (l) bgt 00111110 disp (h) disp (l) ble 00111111 disp (h) disp (l) jmp @rn 2 00010001 11010rrr jmp @aa:16 3 00010000 address (h) address (l) instruction bytes 377
table a-1 (c) machine language coding [special format: branch instruction] (cont) operation code 1 2 3 4 jmp @(d:8,rn) 3 00010001 11100rrr disp jmp @(d:16,rn) 4 00010001 11110rrr disp (h) disp (l) bsr d:8 2 00001110 disp bsr d:16 3 00011110 disp (h) disp (l) jsr @rn 2 00010001 11011rrr jsr @aa:16 3 00011000 address (h) address (l) jsr @(d:8,rn) 3 00010001 11101rrr disp jsr @(d:16,rn) 4 00010001 11111rrr disp (h) disp (l) rts 1 00011001 rtd #xx:8 2 00010100 data rtd #xx:16 3 00011100 data (h) data (l) scb/cc rn,disp scb/f 3 00000001 10111rrr disp scb/ne 00000110 10111rrr disp scb/eq 00000111 10111rrr disp pjmp @aa:24 4 00010011 page address (h) address (l) pjmp @rn 2 00010001 11000rrr pjsr @aa:24 4 00000011 page address (h) address (l) pjsr @rn 2 00010001 11001rrr prts 2 00010001 00011001 prtd #xx:8 3 00010001 00010100 data prtd #xx:16 4 00010001 00011100 data (h) data (l) table a-1 (d) machine language coding [special format: system control instructions] operation code 1 2 3 4 trapa #xx 2 00001000 0001 #vec trap/vs 1 00001001 rte 1 00001010 link fp,#xx:8 2 00010111 data link fp,#xx:16 3 00011111 data (h) data (l) unlk fp 1 00001111 sleep 1 00011010 nop 1 00000000 instruction bytes instruction bytes 378
a.3 operation code map t ables a-2 through a-6 are maps of the operation codes. t able a-2 shows the meaning of the first byte of the instruction code, indicating both operation codes and addressing modes. t ables a-2 through a-6 indicate the meanings of operation codes in the second and third bytes. table a-2 operation codes in byte 1 notes: h'11 is the first operation code byte of the following instructions: jmp, jsr, pjsr (register indirect addressing mode) jmp, jsr (register indirect addressing mode with displacement) prts, prtd (all addressing modes) * references to tables a-3 through a-6 indicate that the instruction code has one or more additional bytes, described in those tables. 2 bra brn bhi bls bcc bcs bne beq bvc bvs bpl bmi bge blt bgt ble d:8 3 bra brn bhi bls bcc bcs bne beq bvc bvs bpl bmi bge blt bgt ble d:16 cmp:e #xx:8, rn cmp:i #xx:16, rn 4 r0 r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7 5 mov:e #xx:8, rn mov:i #xx:16, rn 6 mov:l.b @aa:8, rn mov:l.w @aa:8, rn 7 mov:s.b rn, @aa:8 mov:s.w rn, @aa:8 8 mov:f.b @ (d:8, r6), rn mov:f.w @ (:8, r6), rn 9 mov:f.b rn, @ (d:8, r6) mov:f.w rn, @ (d:8,r6) a rn (byte) rn (word) b @?n (byte) @?n (word) c @rn+ (byte) @rn+ (word) d @rn (byte) @rn (word) e @(d:8,rn) (byte) @(d:8,rn) (word) f @(d:16,rn) (byte) @(d:16,rn) (word) 0 1 2 3 4 5 6 7 8 9 a b c d e f nop scb/f ldm pjsr #xx:8 #aa:8.b scb/ne scb/eq trapa t r a p / v s rte #xx:16 @aa:8.w bsr unlk 0 see @aa:24 see see see see see see d:8 tbl. tbl. tbl. tbl. tbl. tbl. tbl. a-6 a-5 a-4 a-6 a-6 a-5 a-4 jmp see stm pjmp rtd @aa:16.b link jsr rts sleep rtd @aa:16.w bsr link 1 tbl. @aa:24 #xx:8 see #xx:8 #xx:16 see d:16 #xx:16 a-6 tbl. tbl. * a-4 a-4 lo hi see table a-3 see table a-4 see table a-4 see table a-4 see table a-4 see table a-4 see table a-3 see table a-4 see table a-4 see table a-4 see table a-4 see table a-4
table a-3 operation codes in byte 2 (axxx) 0 1 2 3 4 5 6 7 8 9 a b c d e f lo hi 1 2 3 4 5 6 7 8 9 a b c d e f 0 bset (immediate specification of bit number) b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 r0 r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7 swap exts extu clr neg not tst tas shal shar shlr rotl rotr rotxl rotxr see tbl. a-6 * shll add add:q #1 add:q #-1 add:q #2 add:q #-2 adds note: * the operation code is in byte 3, given in table a-6. bset (register indirect specification of bit number) stc subs bclr (register indirect specification of bit number) bnot (register indirect specification of bit number) btst (register indirect specification of bit number) ldc divxu mulxu xch sub or and xor cmp mov addx subx bclr (immediate specification of bit number) bnot (immediate specification of bit number) btst (immediate specification of bit number) note: * prefix code for dadd, dsub, movtpe, and movfpe. the operation code is in byte 3, given in table a-6.
table a-4 operation codes in byte 2 (05xx, 15xx, 0dxx, 1dxx, bxxx, cxxx, dxxx, exxx, fxxx) 0 1 2 3 4 5 6 7 8 9 a b c d e f lo hi 1 2 3 4 5 6 7 8 9 a b c d e f 0 bset (register indirect specification of bit number) clr neg not tst tas shal shar shlr rotl rotr rotxl rotxr see tbl. a-6 * shll add:q #1 add:q #-1 add:q #2 add:q #-2 stc note: * the operation code is in byte 3, given in table a-6. #xx:16 #xx:16 #xx:8 #xx:8 (load) (store) cmp cmp mov mov mov add sub or and xor cmp mov addx subx adds subs bclr (register indirect specification of bit number) bnot (register indirect specification of bit number) btst (register indirect specification of bit number) ldc divxu mulxu bset (immediate specification of bit number) bclr (immediate specification of bit number) bnot (immediate specification of bit number) btst (immediate specification of bit number) note: * prefix code for dadd, dsub, movtpe, and movfpe. the operation code is in byte 3, given in table a-6.
table a-5 operation codes in byte 2 (04xx, 0cxx) 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f lo hi 0 add adds sub subs or orc and andc xor xorc cmp mov ldc addx mulxu subx divxu
table a-6 operation codes in bytes 2 and 3 (11xx, 01xx, 06xx, 07xx, xx00xx) 0 1 2 3 4 5 6 7 8 9 a b c d e f lo hi 1 2 3 4 5 6 7 8 9 a b c d e f 0 #xx:8 #xx:16 prtd movfpe r0 r1 r2 r3 r4 r5 r6 r7 movtpe dadd scb dsub r0 r1 r2 r3 r4 r5 r6 r7 pjmp @rn pjsr @rn jmp @rn jsr @rn jmp @(d:8,rn) jsr @(d:8,rn) jmp @(d:16,rn) jsr @(d:16,rn) prtd prts
a.4 instruction execution cycles tables a-7 (1) through (6) list the number of cycles required by the cpu to execute each instruction in each addressing mode. the meaning of the symbols in the tables is explained below. the values of i, j, and k are used to calculate the number of execution cycles when off-chip memory is accessed for an instruction fetch or operand read/write. the formulas for these calculations are given next. a.4.1 calculation of instruction execution states one state is one system clock cycle (?. when ?= 10 mhz, one state = 100 ns. instruction fetch operand read/write number of states on-chip memory on-chip memory, (value given in table a-7) + general register, (value in table a-8) or no operand on-chip memory module byte (value in table a-7) + or off-chip memory (value in table a-8) + i word (value in table a-7) + (value in table a-8) + 2i off-chip memory on-chip memory, (value given in table a-7) + 2(j + k) general register, or no operand on-chip supporting module byte (value in table a-7) + or off-chip memory i + 2(j + k) word (value in table a-7) + 2(i + j + k) notes: * 1 when the instruction is fetched from on-chip memory (rom or ram), the number of execution states varies by 1 or 2 depending of whether the instruction is stored at an even or odd address. this difference must be noted when software is used for timing, and in other cases in which the exact number of states is important. * 2 if wait states are inserted in access to external memory, add the necessary number of cycles. * 1 * 2 * 2 * 2 384
a.4.2 tables of instruction execution cycles tables a-7 (1) through (6) should be read as shown below: j + k = instruction fetch cycles. instruction rn @rn @(d:8, rn) @(d:16, rn) @?n @rn+ @aa:8 @aa:16 #xx:8 #xx:16 addressing mode add.b add.w add:q.b add:q.w dadd 1 1 2 5 5 6 5 6 5 6 3 1 j 1 1 2 3 1 1 2 3 2 k 3 2 1 2 5 5 6 5 6 5 6 4 2 1 2 7 7 8 7 8 7 8 4 1 2 7 7 8 7 8 7 8 2 i: total number of bytes written and read when operand is in memory. shading in the i column means the operand cannot be in memory. shading indicates addressing modes that cannot be used with this instruction. 4 385
? examples of calculation of number of states required for execution (example 1) instruction fetch from on-chip memory: add:g.w @r0, r1 operand start assembler notation table a-7 + number read/write addr. address code mnemonic table a-8 of states on-chip memory even h'0100 h'd821 add:g.w @r0, r1 5 + 1 6 or general register odd h'0101 h'd821 add:g.w @r0, r1 5 + 0 5 (example 2) instruction fetch from on-chip memory: jsr @r0 branch assembler notation table a-7 + number addr. address code mnemonic table a-8 + 2i of states even h'fc00 h'11d8 jsr @r0 9 + 0 + 2 2 13 odd h'fc01 h'11d8 jsr @r0 9 + 1 + 2 2 14 (example 3) instruction fetch from external memory operand assembler notation table a-7 + number read/write address code mnemonic 2(j + k) of states on-chip memory or h'9002 h'd821 add:g.w @r0, r1 5 + 2 (1 + 1) 9 general register on-chip module h'9002 h'd821 add:g.w @r0, r1 5 + 2 (2 + 1 + 1) 13 or external memory 386
instruction rn @rn @(d:8, rn) @(d:16, rn) @ern @rn+ @aa:8 @aa:16 #xx:8 #xx:16 addressing mode add:g.b , r add:g.w , r add:q.b #xx, add:q.w #xx, adds.b , r adds.w , r addx.b , r addx.w , r and.b , r and.w , r andc #xx, cr bclr.b #xx, bclr.w #xx, bnot.b #xx, bnot.w #xx, bset.b #xx, bset.w #xx, btst.b #xx, btst.w #xx, clr.b clr.w cmp:g.b , r cmp:g.w , r cmp:g.b #xx:8, cmp:g.b #xx:16, 1 1 2 5 5 6 5 6 5 6 3 1 j 1 1 2 3 1 1 2 3 2 k 3 2 1 2 5 5 6 5 6 5 6 4 2 1 2 7 7 8 7 8 7 8 4 1 2 7 7 8 7 8 7 8 1 1 3 5 5 6 5 6 5 6 3 2 1 3 5 5 6 5 6 5 6 4 1 1 2 5 5 6 5 6 5 6 3 2 1 2 5 5 6 5 6 5 6 4 1 1 2 5 5 6 5 6 5 6 3 2 1 2 5 5 6 5 6 5 6 4 1 9 5 2 1 4 7 7 8 7 8 7 8 4 1 4 7 7 8 7 8 7 8 2 1 4 7 7 8 7 8 7 8 4 1 4 7 7 8 7 8 7 8 2 1 4 7 7 8 7 8 7 8 4 1 4 7 7 8 7 8 7 8 1 1 3 5 5 6 5 6 5 6 2 1 3 5 5 6 5 6 5 6 1 1 2 5 5 6 5 6 5 6 2 1 2 5 5 6 5 6 5 6 1 1 2 5 5 6 5 6 5 6 3 2 1 2 5 5 6 5 6 5 6 4 1 2 6 6 7 6 7 6 7 2 3 7 7 8 7 8 7 8 rs can also be specified as the source operand. * d s s d d s d d s d s d s d s d s d d d d d d d s d d d d d s d * * * * * * * * table a-7 instruction execution cycles (1) 387
i j addressing mode rn @rn @(d:8,rn) @(d:16,rn) @-rn @rn+ @aa:8 @aa:16 #xx:8 #xx:16 k cmp:e #xx:8,rd 0 2 cmp:i #xx:16,rd 0 3 dadd 2 4 divxu.b 1 1 20 23 23 24 23 24 23 24 21 divxu.w 2 1 26 29 29 30 29 30 29 30 28 dsub 2 4 exts 1 3 extu 1 3 ldc.b 1 1 3 6 6 7 6 7 6 7 4 ldc.w 2 1 4 7 7 8 7 8 7 8 6 mov.b 1 1 2 5 5 6 5 6 5 6 3 mov.w 2 1 2 5 5 6 5 6 5 6 4 mov.b #xx:8, 1 2 7 7 8 7 8 7 8 mov.w #xx:16, 2 3 8 8 9 8 9 8 9 mov:e #xx:8,rd 0 2 mov:i #xx:16,rd 0 3 mov:l.b @aa:8,rd 1 0 5 mov:l.w @aa:8,rd 2 0 5 mov:s.b rs,@aa:8 1 0 5 mov:s.w rs,@aa:8 2 0 5 mov:f.b @(d:8, r6), rd 1 0 5 mov:f.w @(d:8, r6), rd 2 0 5 instruction 1 1 2 3 1 1 2 3 2 3 mov:f.b rs, @(d:8, r6) 1 0 5 mov:f.w rs, @(d:8, r6) 2 0 5 instruction rn @rn @(d:8, rn) @(d:16, rn) @?n @rn+ @aa:8 @aa:16 #xx:8 #xx:16 addressing mode cmp:e #xx:8, r cmp:i #xx:16, r dadd r , r divxu.b , r divxu.w , r dsub r , r exts r extu r ldc.b , cr ldc.w , cr mov:g.b mov:g.w mov.g.b #xx:8, mov.g.b #xx:16, mov:e #xx:8, r mov:i #xx:16, r mov:l.b @aa:8, r mov:l.w @aa:8, r mov:s.b r ,@aa:8 mov:s.w r ,@aa:8 mov:f.b @(d:8, r6), r mov:f.w @(d:8, r6), r mov:f.b r , @(d:8, r6) mov:f.w r , @(d:8, r6) 0 2 1 j 1 1 2 3 1 1 2 3 2 k 3 0 3 2 4 1 1 20 23 23 24 23 24 23 24 2 1 26 29 29 30 29 30 29 30 2 4 1 3 1 3 1 1 3 6 6 7 6 7 6 7 4 2 1 4 7 7 8 7 8 7 8 6 1 3 2 1 2 5 5 6 5 6 5 6 1 2 7 7 8 7 8 7 8 2 3 8 8 9 8 9 8 9 0 0 1 0 5 2 0 5 1 0 5 2 0 5 1 0 5 2 0 5 1 0 5 2 0 5 1 21 28 2 5 5 6 5 6 5 6 4 2 3 d s d d s d s d s d d d s s d d d s d s d d s s d d table a-7 instruction execution cycles (2) 388
instruction rn @rn @(d:8, rn) @(d:16, rn) @ern @rn+ @aa:8 @aa:16 #xx:8 #xx:16 addressing mode movfpe , r movtpe r , mulxu.b , r mulxu.w , r neg.b neg.w not.b not.w or.b , r or.w , r orc #xx, cr rotl.b rotl.w rotr.b rotr.w rotxl.b rotxl.w rotxr.b rotxr.w shal.b shal.w shar.b shar.w 0 2 13 | 20 13 | 20 14 | 21 13 | 20 13 | 20 14 | 21 1 j 1 1 2 3 1 1 2 3 2 k 3 0 2 13 | 20 13 | 20 14 | 21 13 | 20 14 | 21 13 | 20 14 | 21 1 1 16 19 19 20 19 20 19 20 18 2 1 23 25 25 26 25 26 25 26 25 2 1 2 7 7 8 7 8 7 8 4 1 2 7 8 7 8 7 8 2 1 2 7 7 8 7 8 7 8 1 3 2 1 2 5 5 6 5 6 5 6 1 5 2 1 2 7 7 8 7 8 7 8 4 1 2 7 7 8 7 8 7 8 2 1 2 7 7 8 7 8 7 8 4 1 2 7 7 8 7 8 7 8 2 1 2 4 1 3 2 1 2 4 1 2 2 1 2 4 1 2 2 1 4 1 7 7 8 7 8 7 8 shll.b shll.w 2 1 7 7 8 7 8 7 8 4 1 7 7 8 7 8 7 8 14 | 21 7 4 1 2 7 8 7 8 7 8 1 1 2 5 5 6 5 6 5 6 7 4 9 2 2 2 2 7 7 8 7 8 7 8 7 7 8 7 8 7 8 7 7 8 7 8 7 8 7 7 8 7 8 7 8 7 7 8 7 8 7 8 7 7 8 7 8 7 8 7 7 8 7 8 7 8 d s s d s d s d s d d d d d s d d d d d d d d d d d d d d d table a-7 instruction execution cycles (3) 389
instruction rn @rn @(d:8, rn) @(d:16, rn) @ern @rn+ @aa:8 @aa:16 #xx:8 #xx:16 addressing mode shlr.b shlr.w stc.b cr, stc.w cr, sub.b , r sub.w , r subs.b , r subs.w , r subx.b , r subx.w , r swap r tas tst.b tst.w xch r , r xor.b , r xor.w , r xorc #xx, cr divxu.b divxu.b divxu.w divxu.w divxu.b divxu.w 2 1 2 7 7 8 7 8 7 8 1 j 1 1 2 3 1 1 2 3 2 k 3 4 1 2 1 1 2 7 7 8 7 8 7 8 2 1 2 7 7 8 7 8 7 8 1 1 2 5 5 6 5 6 5 6 3 2 1 2 5 5 6 5 6 5 6 4 1 1 3 5 5 6 5 6 5 6 3 2 1 3 5 5 6 5 6 5 6 4 1 1 2 5 5 6 5 6 5 6 3 2 1 2 5 5 6 5 6 5 6 4 1 9 5 2 1 4 7 7 8 7 8 7 8 1 1 2 5 5 6 5 6 5 6 2 1 2 5 5 6 5 6 5 6 1 4 1 1 2 4 1 4 1 6 1 20 23 23 24 23 24 23 24 1 25 28 28 29 28 29 28 29 1 20 23 23 24 23 24 23 24 27 1 25 28 28 29 28 29 28 29 27 1 1 11 11 12 11 12 11 12 2 1 11 11 12 11 12 11 12 zero divide, minimum mode zero divide, maximum mode zero divide, minimum mode zero divide, maximum mode overflow overflow 21 21 8 8 9 10 7 10 12 6 8 10 11 7 7 8 7 8 7 8 3 5 5 6 5 6 5 6 5 5 6 5 6 5 6 3 4 for register and immediate operands for memory operand ? * ? * d s d d d d s d s d s d s d s d d d d d s d s d s d table a-7 instruction execution cycles (4) 390
instruction (condition) execution cycles i j + k bcc d:8 condition false, branch not taken 3 2 2 5 3 6 4 5 5 5 5 6 5 5 5 6 2 2 3 1 4 5 4 4 4 3 3 6 0 2 7 3 7 9 9 7 6 7 8 9 9 9 10 6 + 4n * 6 7 2 9 9 13 15 8 3 4 8 2 6 + 3n * 2 2 2 2 2 2n 2 2 2 2 4 6 2 2n bcc d:16 bsr jmp jsr ldm link nop rtd rte rts scb sleep stm condition true, branch taken condition false, branch not taken condition true, branch taken d:8 d:16 @aa:16 @rn @(d:8, rn) @(d:16, rn) @aa:16 @rn @(d:8, rn) @(d:16, rn) #xx:8 #xx:16 #xx:8 #xx:16 minimum mode maximum mode condition false, branch not taken count = e1, branch not taken other than the above, branch taken cycles preceding transition to power- down mode * n is the number of registers specified in the register list. table a-7 instruction execution cycles (5) 391
table a-7 instruction execution cycles (6) table a-8 (b) adjusted value (other instructions by addressing modes) table a-8 (a) adjusted value (branch instruction) instruction address adjusted value bsr, jmp, jsr, rts, rtd, rte even 0 trapa, pjmp, pjsr, prts, prtd odd 1 bcc, scb, trap/vs (when branch even 0 is taken) odd 1 instruction (condition) execution cycles j + k trapa minimum mode 17 10 4 4 1 4 4 1 6 5 6 5 5 5 6 22 3 18 23 5 9 8 15 13 12 13 13 2 trap/vs unlk pjmp prts maximum mode v = 0, trap not taken v = 1, trap taken, minimum mode v = 1, trap taken, maximum mode @aa:24 @rn @aa:24 @rn #xx:8 #xx:16 pjsr prtd 6 10 i 6 4 4 4 4 4 instruction mov.b #xx:8, mov.w #xx:16, instruction other than above start address rn @rn @(d:8, rn) @(d:16, rn) @?n @rn+ @aa:8 @aa:16 #xx:8 #xx:16 even even odd even odd 1 2 0 1 0 0 0 0 0 0 0 1 0 2 0 1 1 2 0 1 0 1 2 0 1 0 1 2 0 1 0 1 0 2 0 1 1 2 0 1 0 odd 1 1 1 1 1 1 1 392
appendix b register field b.1 register addresses and bit names addr. addr. (upper (lower register bit names byte) byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'80 p1ddr p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr port 1 h'81 p2ddr p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr port 2 h'82 p1dr p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 port 1 h'83 p1dr p2 4 p2 3 p2 2 p2 1 p2 0 port 2 h'84 p3ddr p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr port 3 h'85 p4ddr p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr port 4 h'86 p3dr p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 port 3 h'fe h'87 p4dr p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 port 4 h'88 p5ddr p5 7 ddr p5 6 ddr p5 5 ddr p5 4 ddr p5 3 ddr p5 2 ddr p5 1 ddr p5 0 ddr port 5 h'89 p6ddr p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr port 6 h'8a p5dr p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 port 5 h'8b p6dr p6 3 p6 2 p6 1 p6 0 port 6 h'8c p7ddr p7 7 ddr p7 6 ddr p7 5 ddr p7 4 ddr p7 3 ddr p7 2 ddr p7 1 ddr p7 0 ddr port 7 h'8d h'8e p7dr p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 port 7 h'8f p8dr p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 port 8 h'90 tcr icie ocieb ociea ovie oeb oea cks1 cks0 h'91 tcsr icf ocfb ocfa ovf olvlb olvla iedg cclra h'92 frc(h) h'93 frc(l) h'94 ocra(h) h'95 ocra(l) h'96 ocrb(h) h'fe h'97 ocrb(l) h'98 icr(h) frt 1 h'99 icr(l) h'9a h'9b h'9c h'9d h'9e h'9f note: (continued on next page) frt1: free-running timer channel 1 393
(continued from preceding page) addr. addr. (upper (lower register bit names byte) byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'a0 tcr icie ocieb ociea ovie oeb oea cks1 cks0 h'a1 tcsr icf ocfb ocfa ovf olvlb olvla iedg cclra h'a2 frc(h) h'a3 frc(l) h'a4 ocra(h) h'a5 ocra(l) h'a6 ocrb(h) h'fe h'a7 ocrb(l) h'a8 icr(h) frt2 h'a9 icr(l) h'aa h'ab h'ac h'ad h'ae h'af h'b0 tcr icie ocieb ociea ovie oeb oea cks1 cks0 h'b1 tcsr icf ocfb ocfa ovf olvlb olvla iedg cclra h'b2 frc(h) h'b3 frc(l) h'b4 ocra(h) h'b5 ocra(l) h'b6 ocrb(h) h'fe h'b7 ocrb(l) h'b8 icr(h) frt 3 h'b9 icr(l) h'ba h'bb h'bc h'bd h'be h'bf notes: (continued on next page) frt2: free-running timer channel 2 frt3: free-running timer channel 3 394
395 (continued from preceding page) addr. addr. (upper (lower register bit names byte) byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'c0 tcr oe os cks2 cks1 cks0 h'c1 dtr pwm1 h'c2 tcnt h'c3 h'c4 tcr oe os cks2 cks1 cks0 h'c5 dtr pwm2 h'c6 tcnt h'fe h'c7 h'c8 tcr oe os cks2 cks1 cks0 h'c9 dtr pwm3 h'ca tcnt h'cb h'cc h'cd h'ce h'cf h'd0 tcr cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 h'd1 tcsr cmfb cmfa ovf os3 os2 os1 os0 h'd2 tcora h'd3 tcorb tmr h'd4 tcnt h'd5 h'd6 h'fe h'd7 h'd8 smr c/a chr pe o/e stop cks1 cks0 h'd9 brr h'da scr tie rie te re cke1 cke0 h'db tdr sci1 h'dc ssr tdre rdrf orer fer per h'dd rdr h'de h'df notes: (continued on next page) pwm1: pulse-width modulation timer channel 1 pwm2: pulse-width modulation timer channel 2 pwm3: pulse-width modulation timer channel 3 tmr: 8-bit timer sci1: serial communication interface 1
396 (continued from preceding page) addr. addr. (upper (lower register bit names byte) byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'e0 addra(h) ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 h'e1 addra(l) ad 1 ad 0 h'e2 addrb(h) ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 h'e3 addrb(l) ad 1 ad 0 h'e4 addrc(h) ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 h'e5 addrc(l) ad 1 ad 0 a/d h'e6 addrd(h) ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 h'fe h'e7 addrd(l) ad 1 ad 0 h'e8 adcsr adf adie adst scan cks ch2 ch1 ch0 h'e9 h'ea h'eb h'ec tcsr * ovf wt/it tme cks2 cks1 cks0 wdt h'ed tcnt * h'ee h'ef h'f0 smr c/a chr pe o/e stop cks2 cks0 h'f1 brr h'f2 scr tie rie te re oke1 oke2 h'f3 tdr sci2 h'f4 ssr tdre rdrf orer fer h'f5 rdr h'f6 h'fe h'f7 h'f8 h'f9 h'fa h'fb h'fc syscr1 irq 1 e irq 0 e nmieg brle port 1 h'fd syscr2 irq 5 e irq 4 e irq 3 e irq 2 e p6pwme p9pwme p9sci2e port 6,9 h'fe p9ddr p9 7 ddr p9 6 ddr p9 5 ddr p9 4 ddr p9 3 ddr p9 2 ddr p9 1 ddr p9 0 ddr port 9 h'ff p9dr p9 7 p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 notes: (continued on next page) a/d: analog-to-digital converter wdt: watchdog timer sci2: serial communication interface 2 * read addresses are shown. write addresses of both tcsr and tcnt are h'feed. see section 13.2.4, ?otes on register access?for details.
397 (continued from preceding page) addr. addr. (upper (lower register bit names byte) byte) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'00 ipra irq 0 irq 1 h'01 iprb irq 2 /irq 3 irq 4 /irq 5 h'02 iprc frt1 frt2 h'03 iprd frt3 8 bit timer h'04 ipre sci1 sci2 h'05 iprf a/d h'06 h'ff h'07 intc h'08 dtea irq 0 irq 1 h'09 dteb irq 3 irq 2 irq 5 irq 4 h'0a dtec ocib1 ocia1 ici1 ocib2 ocia2 ici2 h'0b dted ocib3 ocia3 ici3 cmib cmia h'0c dtee txi1 rxi1 txi2 rxi2 h'0d dtef adi h'0e h'0f h'10 wcr wms1 wms0 wc1 wc0 wsc h'11 ramcr rame ram h'12 mdcr mds2 mds1 mds0 h'13 sbycr ssby h'14 wcr wdt h'15 rstcsr wrst rstoe h'16 h'ff h'17 h'18 h'19 h'1a h'1b h'1c h'1d h'1e h'1f notes: intc: interrupt controller wsc: wait state controller wdt: watchdog timer
398 syscr1?ystem control register 1 h'fefc port 1 bit 7 6 5 4 3 2 1 0 irq 1 e irq 0 e nmieg brle initial value 1 0 0 0 0 1 1 1 read/write r/w r/w r/w r/w nonmaskable interrupt edge 0 an nmi request is generated on the falling edge of the nmi pin input. 1 an nmi request is generated on the rising edge of the nmi pin input. bus release enable 0 p1 2 and p1 3 are i/o ports. 1 p1 2 is the back output pin. p1 3 is the breq input pin. register name name of the on-chip supporting module names of the bits. dashes (? indicate reserved bits. address to which the register is mapped acronym of the register bit numbers initial bit values full name of the bit functions of the bit settings interrupt request 0 enable 0 p1 5 is an i/o port; irq 0 input is disabled. 1 p1 5 is the irq 0 input pin. interrupt request 1 enable 0 p1 6 is an i/o port; irq 1 input is disabled. 1 p1 6 is the irq 1 input pin. t ype of access permitted r read only w write only r/w both read and write b.2 register descriptions
p1ddr?ort 1 data direction register h'fe80 port 1 bit 7 6 5 4 3 2 1 0 p1 7 ddr p1 6 ddr p1 5 ddr p1 4 ddr p1 3 ddr p1 2 ddr p1 1 ddr p1 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w port 1 input/output selection 0 input port 1 output port p1dr?ort 1 data register h'fe82 port 1 bit 7 6 5 4 3 2 1 0 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 initial value 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r r p2ddr?ort 2 data direction register h'fe81 port 2 bit 7 6 5 4 3 2 1 0 p2 4 ddr p2 3 ddr p2 2 ddr p2 1 ddr p2 0 ddr initial value 1 1 1 0 0 0 0 0 read/write w w w w w port 2 input/output selection 0 input port 1 output port 399
p2dr?ort 2 data register h'fe83 port 2 bit 7 6 5 4 3 2 1 0 p2 4 p2 3 p2 2 p2 1 p2 0 initial value 1 1 1 0 0 0 0 0 read/write r/w r/w r/w r/w r/w p3dr?ort 3 data register h'fe86 port 3 bit 7 6 5 4 3 2 1 0 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p3ddr?ort 3 data direction register h'fe84 port 3 bit 7 6 5 4 3 2 1 0 p3 7 ddr p3 6 ddr p3 5 ddr p3 4 ddr p3 3 ddr p3 2 ddr p3 1 ddr p3 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w p4ddr?ort 4 data direction register h'fe85 port 4 bit 7 6 5 4 3 2 1 0 p4 7 ddr p4 6 ddr p4 5 ddr p4 4 ddr p4 3 ddr p4 2 ddr p4 1 ddr p4 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w port 3 input/output selection 0 input port 1 output port port 4 input/output selection 0 input port 1 output port 400
401 p4dr?ort 4 data register h'fe87 port 4 bit 7 6 5 4 3 2 1 0 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p5dr?ort 5 data register h'fe8a port 5 bit 7 6 5 4 3 2 1 0 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p5ddr?ort 5 data direction register h'fe88 port 5 bit 7 6 5 4 3 2 1 0 p5 7 ddr p5 6 ddr p5 5 ddr p5 4 ddr p5 3 ddr p5 2 ddr p5 1 ddr p5 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w p6ddr?ort 6 data direction register h'fe89 port 6 bit 7 6 5 4 3 2 1 0 p6 3 ddr p6 2 ddr p6 1 ddr p6 0 ddr initial value 1 1 1 1 0 0 0 0 read/write w w w w port 5 input/output selection 0 input port 1 output port port 6 input/output selection 0 input port 1 output port
402 p6dr?ort 6 data register h'fe8b port 6 bit 7 6 5 4 3 2 1 0 p6 3 p6 2 p6 1 p6 0 initial value 1 1 1 1 0 0 0 0 read/write r/w r/w r/w r/w p7dr?ort 7 data register h'fe8e port 7 bit 7 6 5 4 3 2 1 0 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w p8dr?ort 8 data register h'fe8f port 8 bit 7 6 5 4 3 2 1 0 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 read/write r r r r r r r r p7ddr?ort 7 data direction register h'fe8c port 7 bit 7 6 5 4 3 2 1 0 p7 7 ddr p7 6 ddr p7 5 ddr p7 4 ddr p7 3 ddr p7 2 ddr p7 1 ddr p7 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w port 7 input/output selection 0 input port 1 output port
403 tcr?imer control register h'fe90 frt1 bit 7 6 5 4 3 2 1 0 icie ocieb ociea ovie oeb oea cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w output enable a 0 compare-a output is disabled. 1 compare-a output is enabled. output enable b 0 compare-b output is disabled. 1 compare-b output is enabled. timer overflow interrupt enable 0 overflow interrupt request is disabled. 1 overflow interrupt request is enabled. output compare interrupt enable a 0 compare-match a interrupt request is disabled. 1 compare-match a interrupt request is enabled. output compare interrupt enable b 0 compare-match b interrupt request is disabled. 1 compare-match b interrupt request is enabled. input capture interrupt enable 0 input capture interrupt is disabled. 1 input capture interrupt is enabled. clock select 00 internal clock source: ? 01 internal clock source: ? 10 internal clock source: ?2 11 external clock source: counted on rising edge
404 tcsr?imer control/status register h'fe91 frt1 bit 7 6 5 4 3 2 1 0 icf ocfb ocfa ovf olvlb olvla iedg cclra initial value 0 0 0 0 0 0 0 0 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/w r/w r/w r/w input edge select 0 count is captured on falling edge of input capture signal (fti). 1 count is captured on rising edge of input capture signal. output level a 0 compare-match a causes 0 output. 1 compare-match a causes 1 output. output level b 0 compare-match b causes 0 output. 1 compare-match b causes 1 output. timer overflow 0 cleared from 1 to 0 when cpu reads ovf = 1, then writes 0 in ovf. 1 set to 1 when frc changes from h'ffff to h'0000. output compare flag a 0 cleared from 1 to 0 when: 1. cpu reads ocfa = 1, then writes 0 in ocfa. 2. ocia interrupt is served by dtc. 1 set to 1 when frc = ocra. output compare flag b 0 cleared from 1 to 0 when: 1. cpu reads ocfb = 1, then writes 0 in ocfb. 2. ocib interrupt is served by dtc. 1 set to 1 when frc = ocrb. input capture flag 0 cleared from 1 to 0 when: 1. cpu reads icf = 1, then writes 0 in icf. 2. ici interrupt is served by dtc. 1 set to 1 when input capture signal is received and frc count is copied to icr. counter clear a 0 frc count is not cleared. 1 frc count is cleared by compare- match a. * only writing of a 0 to clear the flag is enabled.
405 frc (h and l)?ree-running counter h'fe92, h'fe93 frt 1 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w count value ocra (h and l)?utput compare register a h'fe94, h'fe95 frt 1 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w continually compared with frc. ocfa is set to 1 when ocra = frc. ocrb (h and l)?utput compare register b h'fe96, h'fe97 frt 1 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w continually compared with frc. ocfb is set to 1 when ocrb = frc. icr (h and l)?nput capture register h'fe98, h'fe99 frt 1 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r contains frc count captured when external input capture signal changes.
406 tcr?imer control register h'fea0 frt 2 bit 7 6 5 4 3 2 1 0 icie ocieb ociea ovie oeb oea cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for frt1. tcsr?imer control/status register h'fea1 frt 2 bit 7 6 5 4 3 2 1 0 icf ocfb ocfa ovf olvlb olvla iedg cclra initial value 0 0 0 0 0 0 0 0 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/w r/w r/w r/w note: bit functions are the same as for frt1. * only writing of a 0 to clear the flag is enabled. frc (h and l)?ree-running counter h'fea2, h'fea3 frt 2 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for frt1.
ocra (h and l)?utput compare register a h'fea4, h'fea5 frt 2 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for frt1. ocrb (h and l)?utput compare register b h'fea6, h'fea7 frt 2 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for frt1. icr (h and l)?nput capture register h'fea8, h'fea9 frt 2 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r note: bit functions are the same as for frt1. tcr?imer control register h'feb0 frt 3 bit 7 6 5 4 3 2 1 0 icie ocieb ociea ovie oeb oea cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for frt1. 407
tcsr?imer control/status register h'feb1 frt 3 bit 7 6 5 4 3 2 1 0 icf ocfb ocfa ovf olvlb olvla iedg cclra initial value 0 0 0 0 0 0 0 0 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/w r/w r/w r/w note: bit functions are the same as for frt1. * only writing of 0 to clear the flag is enabled. frc (h and l)?ree-running counter h'feb2, h'feb3 frt 3 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for frt1. ocra (h and l)?utput compare register a h'feb4, h'feb5 frt 3 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for frt1. 408
ocrb (h and l)?utput compare register b h'feb6, h'feb7 frt 3 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for frt1. icr (h and l)?nput capture register h'feb8, h'feb9 frt 3 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r note: bit functions are the same as for frt1. 409
410 tcr?imer control register h'fec0 pwm1 bit 7 6 5 4 3 2 1 0 oe os cks2 cks1 cks0 initial value 0 0 1 1 1 0 0 0 read/write r/w r/w r/w r/w r/w clock select (values when ?= 10mhz) internal reso- pwm pwm clock freq. lution period frequency 000 ?2 200 ns 50 s 20 khz 001 ?8 800 ns 200 s 5 khz 010 ?32 3.2 s 800 s 1.25 khz 011 ?128 12.8 s 3.2 ms 312.5 khz 100 ?256 25.6 s 6.4 ms 156.3 hz 101 ?1024 102.4 s 25.6 ms 39.1 hz 110 ?2048 204.8 s 51.2 ms 19.5 hz 111 ?4096 409.6 s 102.4 ms 9.8 hz output enable 0 pwm output disabled; tcnt cleared to h'00 and stops. 1 pwm output enabled; tcnt runs. output select 0 positive logic 1 negative logic dtr?uty register h'fec1 pwm1 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w pulse duty factor
411 tcnt?imer counter h'fec2 pwm1 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * * write function is for test purposes only. writing to this register during normal operation may have unpredictable effects count value (runs from h'00 to h'f9, then repeats from h'00) tcr?imer control register h'fec4 pwm2 bit 7 6 5 4 3 2 1 0 oe os cks2 cks1 cks0 initial value 0 0 1 1 1 0 0 0 read/write r/w r/w r/w r/w r/w note: bit functions are the same as for pwm1. dtr?uty register h'fec5 pwm2 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for pwm1.
412 tcnt?imer counter h'fec6 pwm2 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * note: bit functions are the same as for pwm1. * write function is for test purposes only. writing to this register during normal operation may have unpredictable effects tcr?imer control register h'fec8 pwm3 bit 7 6 5 4 3 2 1 0 oe os cks2 cks1 cks0 initial value 0 0 1 1 1 0 0 0 read/write r/w r/w r/w r/w r/w note: bit functions are the same as for pwm1. dtr?uty register h'fec9 pwm3 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for pwm1.
tcnt?imer counter h'feca pwm3 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * note: bit functions are the same as for pwm1. * write function is for test purposes only. writing to this register during normal operation may have unpredictable effects. 413
414 tcr?imer control register h'fed0 tmr bit 7 6 5 4 3 2 1 0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w counter clear 0 0 counter is not cleared. 0 1 cleared by compare-match a. 1 0 cleared by compare-match b. 1 1 cleared on rising edge of external reset input. clock select 0 0 0 no clock source; timer stops. 0 0 1 internal clock source: ?8, counted on falling edge. 0 1 0 internal clock source: ?64, counted on falling edge. 0 1 1 internal clock source: ?1024, counted on falling edge. 1 0 0 no clock source; timer stops. 1 0 1 external clock source, counted on rising edge. 1 1 0 external clock source, counted on falling edge. 1 1 1 external clock source, counted on both rising and falling edges. timer overflow interrupt enable 0 overflow interrupt request is disabled. 1 overflow interrupt request is enabled. compare-match interrupt enable a 0 compare-match a interrupt request is disabled. 1 compare-match a interrupt request is enabled. compare-match interrupt enable b 0 compare-match b interrupt request is disabled. 1 compare-match b interrupt request is enabled.
415 tcsr?imer control/status register h'fed1 tmr bit 7 6 5 4 3 2 1 0 cmfb cmfa ovf os3 * 2 os2 * 2 os1 * 2 os0 * 2 initial value 0 0 0 1 0 0 0 0 read/write r/(w) * 1 r/(w) * 1 r/(w) * 1 r/w r/w r/w r/w output select 0 0 no change on compare-match b. 0 1 output 0 on compare-match b. 1 0 output 1 on compare-match b. 1 1 invert (toggle) output on compare-match b. output select 0 0 no change on compare-match a. 0 1 output 0 on compare-match a. 1 0 output 1 on compare-match a. 1 1 invert (toggle) output on compare-match a. timer overflow flag 0 cleared from 1 to 0 when cpu reads ovf = 1, then writes 0 in ovf. 1 set to 1 when tcnt changes from h'ff to h'00. compare-match flag b 0 cleared from 1 to 0 when: 1. cpu reads cmfb = 1, then writes 0 in cmfb. 2. cmb interrupt is served by the dtc. 1 set to 1 when tcnt = tcorb. *1 only writing of 0 to clear the flag is enabled. *2 when all four bits (os3 to os0) are cleared to 0, output is disabled. compare-match flag a 0 cleared from 1 to 0 when: 1. cpu reads cmfa = 1, then writes 0 in cmfa. 2. cma interrupt is served by the dtc. 1 set to 1 when tcnt = tcora.
416 tcora?ime constant register a h'fed2 tmr bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w the cmfa bit is set to 1 when tcora = tcnt. tcorb?ime constant register b h'fed3 tmr bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w the cmfb bit is set to 1 when tcorb = tcnt. tcnt?imer counter h'fed4 tmr bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w count value
417 smr?erial mode register h'fed8 sci1 bit 7 6 5 4 3 2 1 0 c/a chr pe o/e stop cks1 cks0 initial value 0 0 0 0 0 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w stop bit length 0 one stop bit 1 two stop bits parity mode 0 even parity 1 odd parity character length 0 8-bit data length 1 7-bit data length communication mode 0 asynchronous 1 synchronous parity enable 0 transmit: no parity bit added. receive: parity bit not checked. 1 transmit: parity bit added. receive: parity bit checked. clock select 0 0 ?clock 0 1 ?4 clock 1 0 ?16 clock 1 1 ?64 clock
brr?it rate register h'fed9 sci1 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w constant that determines the baud rate scr?erial control register h'feda sci1 bit 7 6 5 4 3 2 1 0 tie rie te re cke1 cke0 initial value 0 0 0 0 1 1 0 0 read/write r/w r/w r/w r/w r/w r/w clock enable 0 0 sck pin is not used. 1 sck pin is used for output. clock enable 1 0 internal clock 1 external clock, input at sck pin receive enable 0 receive disabled 1 receive enabled transmit enable 0 transmit disabled 1 transmit enabled receive interrupt enable 0 receive interrupt request (rxi) is disabled. 1 receive interrupt request (rxi) is enabled. transmit interrupt enable 0 transmit interrupt request (txi) is disabled. 1 transmit interrupt request (txi) is enabled. 418
tdr?ransmit data register h'fedb sci1 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w transmit data 419
420 ssr?erial status register h'fedc sci1 bit 7 6 5 4 3 2 1 0 tdre rdrf orer fer per initial value 1 0 0 0 0 1 1 1 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * parity error 0 cleared from 1 to 0 when: 1. cpu reads per = 1, then writes 0 in per. 2. the chip is reset or enters a standby mode. 1 set to 1 when a parity error occurs (parity of receive data does not match parity selected by bit). framing error 0 cleared from 1 to 0 when: 1. cpu reads fer = 1, then writes 0 in fer. 2. the chip is reset or enters a standby mode. 1 set to 1 when a framing error occurs (stop bit is 0). overrun error 0 cleared from 1 to 0 when: 1. cpu reads orer = 1, then writes 0 in orer. 2. the chip is reset or enters a standby mode. 1 set to 1 when an overrun error occurs (next data is completely received while rdrf bit is set to 1). receive data register full 0 cleared from 1 to 0 when: 1. cpu reads rdrf = 1, then writes 0 in rdrf. 2. rdr is read by the dtc. 3. the chip is reset or enters a standby mode. 1 set to 1 when one character is received normally and transferred from rsr to rdr. * only writing of 0 to clear the flag is enabled. transmit data register empty 0 cleared from 1 to 0 when: 1. cpu reads tdre = 1, then writes 0 in tdre. 2. the dtc writes data in tdr. 1 set to 1 when: 1. the chip is reset or enters a standby mode. 2. data is transferred from tdr to tsr. 3. cpu reads tdre = 0, then clears 0 in te.
rdr?eceive data register h'fedd sci1 bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r receive data addrn (h)?/d data register n (high) h'fee0, h'fee2, h'fee4, h'fee6 (n = a, b, c, d) a/d bit 7 6 5 4 3 2 1 0 ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r upper 8 bits of 10-bit a/d conversion result addrn (l)?/d data register n (low) h'fee1, h'fee3, h'fee5, h'fee7 (n = a, b, c, d) a/d bit 7 6 5 4 3 2 1 0 ad 1 ad 0 initial value 0 0 0 0 0 0 0 0 read/write r r r r r r r r lower 2 bits of 10-bit a/d conversion result 421
422 adcsr?/d control/status register h'fee8 a/d bit 7 6 5 4 3 2 1 0 adf adie adst scan cks ch2 ch1 ch0 initial value 0 0 0 0 0 0 0 0 read/write r/(w) * r/w r/w r/w r/w r/w r/w r/w channel select ch2 ch1 ch0 single mode scan mode 0 0 an 0 an 0 0 1 an 1 an 0 , an 1 1 0 an 2 an 0 to an 2 1 1 an 3 an 0 to an 3 0 0 an 4 an 4 0 1 an 5 an 4 , an 5 1 0 an 6 an 4 to an 6 1 1 an 7 an 4 to an 7 0 1 clock select 0 conversion time = 274 states 1 conversion time = 138 states scan mode 0 single mode 1 scan mode a/d start 0 a/d conversion is halted. 1 1. single mode: one a/d conversion is performed, then this bit is automatically cleared to 0. 2. scan mode: a/d conversion starts and continues cyclically on all selected channels until 0 is written in this bit. a/d interrupt enable 0 the a/d interrupt request (adi) is disabled. 1 the a/d interrupt request (adi) is enabled. * only writing of 0 to clear the flag is enabled. a/d end flag 0 cleared from 1 to 0 when: 1. the chip is reset or enters a standby mode. 2. cpu reads adf = 1, then writes 0 in adf. 3. dtc is served by adi. 1 set to 1 at the following times: 1. single mode: at the completion of a/d conversion. 2. scan mode: when all selected channels have been converted.
adcr?/d control register h'fee9 a/d bit 7 6 5 4 3 2 1 0 trge initial value 0 1 1 1 1 1 1 1 read/write r/w trigger enable 0 the a/d external trigger is disabled. 1 the a/d external trigger is enabled. a/d conversion starts on the falling edge of adtrg. 423
424 tcsr?imer status/control register h'feec *1 , h'feed *2 wdt bit 7 6 5 4 3 2 1 0 ovf wt/it tme cks2 cks1 cks0 initial value 0 0 0 1 1 0 0 0 read/write r/(w) * 3 r/w r/w r/w r/w r/w timer enable 0 timer is disabled. ? tcnt is initialized to h'00 and stopped. 1 timer is enabled. ? tcnt starts incrementing. ? cpu interrupt request is enabled. timer mode select 0 interval timer mode (irq 0 interrupt request) 1 watchdog timer mode (nmi interrupt request) *1 read address *2 write address *3 only writing of 0 to clear the flag is enabled. *4 times in parentheses are the times for tcnt to increment from h'00 to h'ff and change to h'00 again when ?= 10 mhz. overflow flag 0 cleared from 1 to 0 when cpu reads ovf = 1, then wtites 0 in ovf. 1 set to 1 when tcnt changes from h'ff to h'00. clock select 0 0 0 ?2 (51.2 s) * 4 0 0 1 ?32 (819.2 s) 0 1 0 ?64 (1.6 ms) 0 1 1 ?128 (3.3 ms) 1 0 0 ?256 (6.6 ms) 1 0 1 ?512 (13.1 ms) 1 1 0 ?2048 (52.4 ms) 1 1 1 ?4096 (104.9 ms)
tcnt?imer counter h'feed wdt bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w count value smr?erial mode register h'fef0 sci2 bit 7 6 5 4 3 2 1 0 c/a chr pe o/e stop cks1 cks0 initial value 0 0 0 0 0 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for sci1. brr?it rate register h'fef1 sci2 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for sci1. scr?erial control register h'fef2 sci2 bit 7 6 5 4 3 2 1 0 tie rie te re cke1 cke0 initial value 0 0 0 0 1 1 0 0 read/write r/w r/w r/w r/w r/w r/w note: bit functions are the same as for sci1. 425
tdr?ransmit data register h'fef3 sci2 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for sci1. ssr?erial status register h'fef4 sci2 bit 7 6 5 4 3 2 1 0 tdre rdrf orer fer per initial value 0 0 0 0 0 1 1 1 read/write r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * note: bit functions are the same as for sci1. * only writing of 0 to clear the flag is enabled. rdr?eceive data register h'fef5 sci2 bit 7 6 5 4 3 2 1 0 initial value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w note: bit functions are the same as for sci1. 426
syscr1?ystem control register 1 h'fefc port 1 bit 7 6 5 4 3 2 1 0 irq 1 e irq 0 e nmieg brle initial value 1 0 0 0 0 1 1 1 read/write r/w r/w r/w r/w nonmaskable interrupt edge 0 an nmi request is generated on the falling edge of the nmi pin input. 1 an nmi request is generated on the rising edge of the nmi pin input. bus release enable 0 p1 2 and p1 3 are i/o ports. 1 p1 2 is the back output pin and p1 3 is the breq input pin. interrupt request 0 enable 0 p1 5 is an i/o port; irq 0 input is disabled. 1 p1 5 is the irq 0 input pin. interrupt request 1 enable 0 p1 6 is an i/o port; irq 1 input is disabled. 1 p1 6 is the irq 1 input pin. 427
428 syscr2?ystem control register 2 h'fefd port6, port9 bit 7 6 5 4 3 2 1 0 irq 5 e irq 5 e irq 5 e irq 5 e p6pwme p9pwme p9sci2e initial value 1 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w port 9 pwm enable 0 p9 2 , p9 3 , and p9 4 cannot be used for pwm output. 1 p9 2 , p9 3 , and p9 4 can be used for pwm output (see port 9 pin functions). port 6 pwm enable 0 p6 1 , p6 2 , and p6 3 cannot be used for pwm output. 1 p6 1 , p6 2 , and p6 3 can be used for pwm output (see port 6 pin functions). interrupt request 4 enable 0 p6 2 is not used for irq 4 signal input. 1 p6 2 is used for irq 4 signal input. interrupt request 3 enable 0 p6 1 is not used for irq 3 signal input. 1 p6 1 is used for irq 3 signal input. interrupt request 2 enable 0 p6 0 is not used for irq 2 signal input. 1 p6 0 is used for irq 2 signal input. interrupt request 5 enable 0 p6 3 is not used for irq 5 signal input. 1 p6 3 is used for irq 5 signal input. por t 9 sci2 enable 0 p9 2 , p9 3 , and p9 4 cannot be used for serial communication. 1 p9 2 , p9 3 , and p9 4 can be used for serial communication (see port 9 pin functions).
ipra?nterrupt priority register a h'ff00 intc bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r r/w r/w r/w irq 0 interrupt priority level (0 to 7) irq 1 interrupt priority level (0 to 7) iprb?nterrupt priority register b h'ff01 intc bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r r/w r/w r/w irq 2 and irq 3 interrupt priority level (0 to 7) irq 4 and irq 5 interrupt priority level (0 to 7) p9ddr?ort 9 data direction register h'fefe port 9 bit 7 6 5 4 3 2 1 0 p9 7 ddr p9 6 ddr p9 5 ddr p9 4 ddr p9 3 ddr p9 2 ddr p9 1 ddr p9 0 ddr initial value 0 0 0 0 0 0 0 0 read/write w w w w w w w w port 9 input/output selection 0 input port 1 output port p9dr?ort 9 data register h'feff port 9 bit 7 6 5 4 3 2 1 0 p9 7 p9 6 p9 5 p9 4 p9 3 p9 2 p9 1 p9 0 initial value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 429
iprc?nterrupt priority register c h'ff02 intc bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r r/w r/w r/w 16-bit frt2 interrupt priority level (0 to 7) 16-bit frt1 interrupt priority level (0 to 7) iprd?nterrupt priority register d h'ff03 intc bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r r/w r/w r/w 8-bit timer interrupt priority level (0 to 7) 16-bit frt3 interrupt priority level (0 to 7) ipre?nterrupt priority register e h'ff04 intc bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r r/w r/w r/w sci1 interrupt priority level (0 to 7) sci2 interrupt priority level (0 to 7) 430
dteb?ata transfer enable register b h'ff09 intc bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r r/w r/w r/w irq 2 0 served by cpu 1 served by dtc irq 5 0 served by cpu 1 served by dtc irq 3 0 served by cpu 1 served by dtc irq 4 0 served by cpu 1 served by dtc dtea?ata transfer enable register a h'ff08 intc bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r r/w r/w r/w irq 0 0 served by cpu 1 served by dtc irq 1 0 served by cpu 1 served by dtc iprf?nterrupt priority register f h'ff05 intc bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r r/w r/w r/w a/d interrupt priority level (0 to 7) unused 431
dtec?ata transfer enable register c h'ff0a intc bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r r/w r/w r/w ici1 0 served by cpu 1 served by dtc ocia1 0 served by cpu 1 served by dtc ocib1 0 served by cpu 1 served by dtc (frt1) (frt2) ici2 0 served by cpu 1 served by dtc ocia2 0 served by cpu 1 served by dtc ocib2 0 served by cpu 1 served by dtc 432
dted?ata transfer enable register d h'ff0b intc bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r r/w r/w r/w ocia3 0 served by cpu 1 served by dtc ici3 0 served by cpu 1 served by dtc ocib3 0 served by cpu 1 served by dtc (frt3) (8-bit timer) cmia 0 served by cpu 1 served by dtc cmib 0 served by cpu 1 served by dtc 433
dtee?ata transfer enable register e h'ff0c intc bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r r/w r/w r/w rxi2 0 served by cpu 1 served by dtc rxi1 0 served by cpu 1 served by dtc txi2 0 served by cpu 1 served by dtc txi1 0 served by cpu 1 served by dtc (sci1) (sci2) dtef?ata transfer enable register f h'ff0d intc bit 7 6 5 4 3 2 1 0 initial value 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r r/w r/w r/w adi 0 served by cpu 1 served by dtc (a/d converter) 434
wcr?ait-state control register h'ff10 wsc bit 7 6 5 4 3 2 1 0 wms1 wms0 wc1 wc0 initial value 1 1 1 1 0 0 1 1 read/write r/w r/w r/w r/w wait count 1 and 0 0 0 no wait states (t w ) are inserted. 0 1 1 w ait states are inserted. 1 0 2 w ait states are inserted. 1 1 3 wait state is inserted. wait mode select 1 and 0 0 0 programmable wait mode 0 1 no wait states are inserted, regardless of the wait count. 1 0 pin wait mode 1 1 pin auto-wait mode ramcr?am control register h'ff11 ram bit 7 6 5 4 3 2 1 0 rame initial value 1 1 1 1 1 1 1 1 read/write r/w ram enable 0 on-chip ram is disabled. 1 on-chip ram is enabled. 435
mdcr?ode control register h'ff12 bit 7 6 5 4 3 2 1 0 mds2 mds1 mds0 initial value 1 1 0 0 0 * * * read/write r r r mode select value input at mode pins * initialized according to the inputs at pins md 2 , md 1 , and md 0 . sbycr?oftware standby control register h'ff13 bit 7 6 5 4 3 2 1 0 ssby initial value 0 1 1 1 1 1 1 1 read/write r/w software standby 0 sleep instruction causes transition to sleep mode. 1 sleep instruction causes transition to software standby mode. rstcsr?eset status/control register h'ff15 wdt bit 7 6 5 4 3 2 1 0 wrst rstoe initial value 0 0 1 1 1 1 1 1 read/write r/(w) * r/w watchdog timer reset 0 cleared from 1 to 0 by software, or by a low input at the res pin. 1 set to 1 when tcnt overflows and a reset signal is generated. reset output enable 0 the reset signal is not output externally. 1 the reset signal is output externally. * software can write a 0 in bit 7 to clear the flag but cannot write a 1. 436
appendix c i/o port schematic diagrams c.1 schematic diagram of port 1 figure c-1 (a) to (g) gives a schematic view of the port 1 input/output circuits. table c-1 (a) port 1 port read (pin p1 0 ) setting port read data ddr = 0 pin value ddr = 1 c r q d p1 ddr 0 wp1d reset wp1d: rp1: write to p1ddr read port 1 internal data bus (pdb8) p1 0 rp1 c r q d p1 ddr 1 wp1d reset wp1d: rp1: write to p1ddr read port 1 internal data bus (pdb9) p1 1 e rp1 figure c-1 (a) schematic diagram of port 1, pin p1 0 figure c-1 (b) schematic diagram of port 1, pin p1 1 437
table c-1 (b) port 1 port read (pin p1 1 ) setting port read data ddr = 0 pin value ddr = 1 e table c-1 (c) port 1 port read (pin p1 2 ) mode setting port read data 1, 2, 3, 4 brle = 1 dr value brle = 0 ddr = 0 pin value ddr = 1 dr value 7 ddr = 0 pin value ddr = 1 dr value rp1 brle back q system control register 1, bit 3 mode 1, 2, 3, or 4 wp1 c r q d p1 dr 2 c r q d p1 ddr 2 wp1d reset reset wp1d: wp1: rp1: write to p1ddr write to port 1 read port 1 internal data bus (pdb10) p1 2 figure c-1 (c) schematic diagram of port 1, pin p1 2 438
table c-1 (d) port 1 port read (pin p1 3 ) mode setting port read data 1, 2, 3, 4 brle = 1 pin value brle = 0 ddr = 0 pin value ddr = 1 dr value 7 ddr = 0 pin value ddr = 1 dr value rp1 breq to cpu p1 3 brle q system control register 1, bit 3 mode 1, 2, 3, or 4 wp1 c r q d p1 dr 3 c r q d p1 ddr 3 reset reset wp1d: wp1: rp1: write to p1ddr write to port 1 read port 1 internal data bus (pdb11) wp1d figure c-1 (d) schematic diagram of port 1, pin p1 3 439
table c-1 (e) port 1 port read (pin p1 4 ) mode setting port read data 1, 2, 3, 4 wms 1 = 1 pin value wms 1 = 0 ddr = 0 pin value ddr = 1 dr value 7 ddr = 0 pin value ddr = 1 dr value rp1 wait to cpu p1 4 fig. c-1 (d) wms1 q wait-state control register, bit 3 mode 1, 2, 3, or 4 wp1 c r q d p1 dr 4 c r q d p1 ddr 4 reset reset wp1d: wp1: rp1: write to p1ddr write to port 1 read port 1 internal data bus (pdb12) wp1d figure c-1 (e) schematic diagram of port 1, pin p1 4 440
table c-1 (f) port 1 port read (pin p1 5 ) setting port read data irq 0 e = 1 pin value irq 0 e = 0 ddr = 0 pin value ddr = 1 dr value rp1 irq to cpu p1 5 irq e q system control register 1, bit 5 wp1 c r q d p1 dr 5 c r q d p1 ddr 5 reset reset wp1d: wp1: rp1: write to p1ddr write to port 1 read port 1 internal data bus (pdb13) wp1d 0 0 figure c-1 (f) schematic diagram of port 1, pin p1 5 441
table c-1 (g) port 1 port read (pin p1 6 ) setting port read data trge or irq 1 e = 1 pin value trge and irq 1 e = 0 ddr = 0 pin value ddr = 1 dr value rp1 irq to cpu p1 6 irq e q system control register 1, bit 6 wp1 c r q d p1 dr 6 c r q d p1 ddr 6 reset reset wp1d: wp1: rp1: write to p1ddr write to port 1 read port 1 internal data bus (pdb14) wp1d 0 1 falling edge detector adtrg to a/d converter trge q a/d control register, bit 7 figure c-1 (g) schematic diagram of port 1, pin p1 6 442
table c-1 (h) port 1 port read (pin p1 7 ) setting port read data 8-bit timer output enable 8-bit timer output value 8-bit timer ddr = 0 pin value output disable ddr = 1 dr value rp1 p1 7 fig. c-1 (g) wp1 8-bit timer module output enable 8-bit timer output wp1d: wp1: rp1: write to p1ddr write to port 1 read port 1 internal data bus (pdb15) c r q d p1 dr 7 c r q d p1 ddr 7 reset reset wp1d figure c-1 (h) schematic diagram of port 1, pin p1 7 443
c.2 schematic diagram of port 2 figure c-2 gives a schematic view of the port 2 input/output circuits. table c-2 port 2 port read mode port read data 1, 2, 3, 4 dr value 7 ddr = 0 pin value ddr = 1 dr value fig. c-2 wp2d: wp2: rp2: n: write to p2ddr write to port 2 read port 2 0, 1, 2, 3, or 4 internal data bus (pdb8 to pdb11) mode 1, 2, 3, or 4 software standby bus release mode 7 mode 1, 2, 3, or 4 rp2 bus control signals p2 n wp2 c r q d p2 dr n c r q d p2 ddr n reset wp2d reset s figure c-2 schematic diagram of port 2 444
c.3 schematic diagram of port 3 figure c-3 gives a schematic view of the port 3 input/output circuits. table c-3 port 3 port read mode port read data 1, 2, 3, 4 always reads 1 7 ddr = 0 pin value ddr = 1 dr value internal data bus (pdb8 to pdb15) wp3d: wp3: rp3: n: write to p3ddr write to port 3 read port 3 0 to 7 wp3d c r q d p3 dr n c r q d p3 ddr n reset wp3 reset data write external address read mode 7 rp3 mode 7 mode 1, 2, 3, or 4 mode 1, 2, 3, or 4 mode 1, 2, 3, or 4 p3 n figure c-3 schematic diagram of port 3 445
c.4 schematic diagram of port 4 figure c-4 gives a schematic view of the port 4 input/output circuits. table c-4 port 4 port read mode port read data 1, 2, 3, 4 dr value 7 ddr = 0 pin value ddr = 1 dr value fig. c-4 wp4d: wp4: rp4: n: write to p4ddr write to port 4 read port 4 0 to 7 internal data bus (pdb8 to pdb15) mode 1, 2, 3, or 4 software standby bus release mode 7 mode 1, 2, 3, or 4 rp4 p4 n wp4 c r q d p4 dr n c r q d p4 ddr n reset wp4d reset s internal address bus (iab0 to iab7) figure c-4 schematic diagram of port 4 446
c.5 schematic diagram of port 5 figure c-5 gives a schematic view of the port 5 input/output circuits. table c-5 port 5 port read mode port read data 1, 3 dr value 2, 4, 7 ddr = 0 pin value ddr = 1 dr value fig. c-5 wp5d: wp5: rp5: n: write to p5ddr write to port 5 read port 5 0 to 7 internal data bus (pdb8 to pdb15) mode 1 or 3 software standby bus release mode 7 mode 1, 2, 3, or 4 rp5 p5 n wp5 c r q d p5 dr n c r q d p5 ddr n reset wp5d reset s internal address bus (iab8 to iab15) mos pull-up mode 1, 2, 3, or 4 figure c-5 schematic diagram of port 5 447
c.6 schematic diagram of port 6 figure c-6 gives a schematic view of the port 6 input/output circuits. table c-6 (a) port 6 port read (pin p6 0 ) mode port read data 3 dr value 1, 2, 4, 7 irq 2 e = 0 ddr = 0 pin value ddr = 1 dr value irq 2 e = 1 pin value wp6d: wp6: rp6: write to p6ddr write to port 6 read port 6 internal data bus (pdb8) mode 3 bus release mode 1, 2, or 7 mode 3 or 4 rp6 p6 0 wp6 c r q d p6 dr 0 c r q d p6 ddr 0 reset wp6d reset s internal address bus (iab16) mos pull-up mode 3 or 4 software standby irq to cpu 2 falling edge detector mode 3 mode 4 q system control register 2, bit 3 irq e 2 figure c-6 (a) schematic diagram of port 6, pin p6 0 448
table c-6 (b) port 6 port read (pin p6 1 to p6 3 ) mode and setting port read data 3 dr value 4 ddr = 0 pin value ddr = 1 dr value 1, 2, 7 irq n e = 1 pin value irqne = 0 p6pwme = 1 pwm output enable pwm output value other than the ddr = 0 pin value above settings ddr = 1 dr value wp6d: wp6: rp6: n: write to p6ddr write to port 6 read port 6 1, 2, or 3 internal data bus (pdb9 to pdb11) mode 3 bus release mode 3, 4 rp6 p6 n wp6 c r q d p6 dr n c r q d p6 ddr n reset wp6d reset s internal address bus (iab17 to iab19) mos pull-up mode 3 or 4 software standby irq , irq , irq to cpu 3 falling edge detector mode 3 mode 4 q system control register 2 irq e to 3 4 5 q p6pwme irq e 5 bit 2 bit 6, 5, or 4 pwm timer module pwm1, pwm2, or pwm3 output enable pwm1, pwm2, or pwm3 output figure c-6 (b) schematic diagram of port 6, pin p6 1 to p6 3 449
c.7 schematic diagram of port 7 figure c-7 (a) to (e) gives a schematic view of the port 7 input/output circuits. table c-7 (a) port 7 port read (pin p7 0 ) setting port read data ddr = 0 pin value ddr = 1 dr value rp7 p7 0 fig. c-7 (a) wp7 8-bit timer module input clock wp7d: wp7: rp7: write to p7ddr write to port 7 read port 7 internal data bus (pdb8) c r q d p7 dr 0 c r1 q d p7 ddr 0 reset reset wp7d figure c-7 (a) schematic diagram of port 7, pin p7 0 450
table c-7 (b) port 7 port read (pins p7 1 , p7 2 ) setting port read data ddr = 0 pin value ddr = 1 dr value rp7 p7 n wp7 free-running timer module counter clock output wp7d: wp7: rp7: n: write to p7ddr write to port 7 read port 7 1 or 2 internal data bus (pdb9 to 10) c r q d p7 dr n c r1 q d p7 ddr n reset reset wp7d output enable output compare signal figure c-7 (b) schematic diagram of port 7, pins p7 1 and p7 2 451
table c-7 (c) port 7 port read (pin p7 3 ) setting port read data ddr = 0 pin value ddr = 1 dr value rp7 p7 3 fig. c-7 (c) wp7 8-bit timer module counter reset input wp7d: wp7: rp7: write to p7ddr write to port 7 read port 7 internal data bus (pdb11) c r q d p7 dr 3 c r1 q d p7 ddr 3 reset reset wp7d free-running timer module input capture signal figure c-7 (c) schematic diagram of port 7, pin p7 3 452
table c-7 (d) port 7 port read (pins p7 4 to p7 6 ) setting port read data output enable output compare output value output disable ddr = 0 pin value ddr = 1 dr value rp7 p7 n wp7 free-running timer module wp7d: wp7: rp7: n: write to p7ddr write to port 7 read port 7 4, 5 or 6 internal data bus (pdb12 to pdb14) c r q d p7 dr n c r q d p7 ddr n reset reset wp7d input capture signal figure c-7 (d) schematic diagram of port 7, pins p7 4 , p7 5 and p7 6 453
table c-7 (e) port 7 port read (pin p7 7 ) setting port read data output enable output compare output value output disable ddr = 0 pin value ddr = 1 dr value rp7 p7 7 fig. c-7 (e) wp7 free-running timer module output enable output compare output wp7d: wp7: rp7: write to p7ddr write to port 7 read port 7 internal data bus (pdb15) c r q d p7 dr 7 c r1 q d p7 ddr 7 reset reset wp7d figure c-7 (e) schematic diagram of port 7, pin p7 7 454
c.8 schematic diagram of port 8 figure c-8 gives a schematic view of the port 8 input circuits. p8 n fig. c-8 rp8 rp8: n: read port 8 0 to 7 a/d converter module input multiplexer internal data bus (pdb8 to pdb15) figure c-8 schematic diagram of port 8 455
c.9 schematic diagram of port 9 figure c-9 (a) to (g) gives a schematic view of the port 9 input/output circuits. table c-9 (a) port 9 port read (pins p9 0 , p9 1 ) setting port read data output enable output compare output value output disable ddr = 0 pin value ddr = 1 dr value rp9 p9 n fig. c-9 (a) wp9 free-running timer module output enable output compare output wp9d: wp9: rp9: n: write to p9ddr write to port 9 read port 9 0 or 1 internal data bus (pdb8, pdb9) c r q d p9 dr n c r q d p9 ddr n reset reset wp9d figure c-9 (a) schematic diagram of port 9, pins p9 0 and p9 1 456
table c-9 (b) port 9 port read (pin p9 2 ) setting port read data (pin p9 2 ) port 9 port 9 sci2 output enable serial transmit data value sci2 pwm sci2 output disable ddr = 0 pin value enable disable ddr = 1 dr value port 9 port 9 pwm output enable pwm1 output value sci2 pwm pwm output disable ddr = 0 pin value disable enalbe ddr = 1 dr value port 9 port 9 pwm and sci2 ddr = 0 pin value sci2 pwm output either enabled ddr = 1 dr value disable disable or disabled port 9 port 9 ddr = 0 pin value sci2 pwm ddr = 1 dr value enable enable rp9 p9 2 wp9 pwm timer module pwm output enable pwm1 output wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 internal data bus (pdb10) c r q d p9 dr 2 c r q d p9 ddr 2 reset reset wp9d sci2 module serial transmit data sci2 output enable q system control register 2 p9pwme bit 1 q system control register 2 p9sci2e bit 0 figure c-9 (b) schematic diagram of port 9, pin p9 2 457
table c-9 (c) port 9 port read (pin p9 3 ) setting port read data (pin p9 3 ) port 9 port 9 sci2 input enable serial receive data value sci2 pwm sci2 input disable ddr = 0 pin value enable disable ddr = 1 dr value port 9 port 9 pwm output enable pwm2 output value sci2 pwm pwm output disable ddr = 0 pin value disable enalbe ddr = 1 dr value port 9 port 9 pwm and sci2 ddr = 0 pin value sci2 pwm input either enabled ddr = 1 dr value disable disable or disabled port 9 port 9 ddr = 0 pin value sci2 pwm ddr = 1 dr value enable enable rp9 p9 3 wp9 pwm output enable pwm2 output wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 internal data bus (pdb11) c r q d p9 dr 3 c r q d p9 ddr 3 reset reset wp9d sci2 module serial receive data sci2 input enable system control register 2 system control register 2 q p9pwme bit 1 q p9sci2e bit 0 pwm timer module figure c-9 (c) schematic diagram of port 9, pin p9 3 458
table c-9 (d) port 9 port read (pin p9 4 ) setting port read data (pin p9 4 ) port 9 port 9 clock input enable input clock value sci2 pwm clock output enable output clock value enable disable clock input and output disable ddr = 0 pin value ddr = 1 dr value port 9 port 9 clock input, clock output, and pwm ddr = 0 pin value sci2 pwm output enabled or disabled ddr = 1 dr value enable enalbe port 9 pwm output enable pwm3 output value sci2 pwm output disable ddr = 0 pin value disable ddr = 1 dr value port 9 port 9 clock input, clock output, and pwm ddr = 0 pin value sci2 pwm output either enabled or disabled ddr = 1 dr value disable disable rp9 p9 4 wp9 pwm timer module pwm output enable pwm3 output wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 internal data bus (pdb12) c r q d p9 dr 4 c r q d p9 ddr 4 reset reset wp9d sci2 module clock output clock output enable system control register 2 system control register 2 q p9pwme bit 1 q p9sci2e bit 0 clock input enable clock input figure c-9 (d) schematic diagram of port 9, pin p9 4 459
table c-9 (e) port 9 port read (pin p9 5 ) setting port read data output enable serial transfer data output disable ddr = 0 pin value ddr = 1 dr value rp9 p9 5 wp9 sci1 module output enable serial transfer data wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 internal data bus (pdb13) c r q d p9 dr 5 c r q d p9 ddr 5 reset reset wp9d figure c-9 (e) schematic diagram of port 9, pin p9 5 460
table c-9 (f) port 9 port read (pin p9 6 ) setting port read data output enable serial transfer data output disable ddr = 0 pin value ddr = 1 dr value rp9 p9 6 wp9 sci1 module input enable wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 internal data bus (pdb14) c r q d p9 dr 6 c r q d p9 ddr 6 reset reset wp9d serial receive data figure c-9 (f) schematic diagram of port 9, pin p9 6 461
table c-9 (g) port 9 port read (pin p9 7 ) setting port read data clock input enable input clock value clock output enable output clock value clock input/output ddr = 0 pin value enable ddr = 1 dr value rp9 p9 7 wp9 sci1 module clock input enable wp9d: wp9: rp9: write to p9ddr write to port 9 read port 9 internal data bus (pdb15) c r q d p9 dr 7 c r q d p9 ddr 7 reset reset wp9d clock output enable clock output clock input figure c-9 (g) schematic diagram of port 9, pin p9 7 462
expanded minimum mode expanded maximum mode single-chip mode mode 1 mode 2 mode 3 mode 4 mode 7 vector tables external memory on-chip ram 2 kbytes register field 384 bytes vector tables on-chip rom 32 kbytes external memory on-chip ram 2 kbytes register field 384 bytes vector tables external memory on-chip ram 2 kbytes register field 384 bytes external memory vector tables on-chip rom 32 kbytes external memory on-chip ram 2 kbytes register field 384 bytes external memory vector tables on-chip rom 32 kbytes h'0000 h'00ff h'0100 h'f67f h'f680 h'fe7f h'fe80 h'ffff h'0000 h'00ff h'0100 h'7fff h'8000 page 0 h'f67f h'f680 h'fe7f h'fe80 h'ffff h'00000 h'001ff h'00200 page 0 h'0f67f h'0f680 h'0fe7f h'0fe80 h'0ffff h'10000 h'1ffff h'f0000 h'fffff h'00000 h'001ff h'00200 h'07fff h'08000 page 0 h'0f67f h'0f680 h'0fe7f h'0fe80 h'0ffff h'10000 page 1 h'1ffff h'f0000 page 15 h'fffff h'0000 h'00ff h'0100 h'7fff page 0 h'f680 h'fe7f h'fe80 h'ffff page 1 page 15 page 0 on-chip ram 2 kbytes register field 384 bytes appendix d memory maps table d-1 h8/534 memory map
expanded minimum mode expanded maximum mode single-chip mode mode 1 mode 2 (preliminary) mode 3 mode 4 mode 7 vector tables external memory on-chip ram 2 kbytes register field 384 bytes vector tables on-chip rom 60 kbytes (reserved) * on-chip ram 2 kbytes register field 384 bytes vector tables external memory on-chip ram 2 kbytes register field 384 bytes external memory vector tables on-chip rom 62 kbytes on-chip ram 2 kbytes register field 384 bytes external memory vector tables on-chip rom 62 kbytes on-chip ram 2 kbytes register field 384 bytes h'0000 h'00ff h'0100 h'f67f h'f680 h'fe7f h'fe80 h'ffff h'0000 h'00ff h'0100 h'ee7f page 0 h'ee80 h'f67f h'f680 h'fe7f h'fe80 h'ffff h'00000 h'001ff h'00200 page 0 h'0f67f h'0f680 h'0fe7f h'0fe80 h'0ffff h'10000 h'1ffff h'f0000 h'fffff h'00000 h'001ff h'00200 page 0 h'0f67f h'0f680 h'0fe7f h'0fe80 h'0ffff h'10000 page 1 h'1ffff h'f0000 page 15 h'fffff h'0000 h'00ff h'0100 page 0 h'f67f h'f680 h'fe7f h'fe80 h'ffff page 1 page 15 page 0 * : reserved for future use as external address space table d-2 h8/536 memory map
appendix e pin states e.1 port state of each pin state table e-1 port state hardware port standby software bus program execution pin name mode reset mode standby mode sleep mode release mode state (normal operation) p1 7 to p1 2 1 input/output port or tmo, irq 1 , irq 0 2 control signal input/ wait, breq, 3 t t keep * 1 keep * 3 keep * 4 output back 4 7 keep * 2 keep input/output port p1 1 /e 1 (ddr = 1) (ddr = 1) (ddr = 1) (ddr = 1) p1 0 / 2 clock ?= h clock output clock output clock output 3 output t e = l (ddr = 0) (ddr = 0) (ddr = 0) 4 (ddr = 0) t t input port 7 t p2 4 to p2 0 1 wr, rd, ds, wr, rd, ds, 2 h t h t r/w, as r/w, as 3 4 7 t keep keep input/output port p3 7 to p3 0 1 d 7 to d 0 2 t t t d 7 to d 0 3 t t 4 7 keep keep input/output port p4 7 to p4 0 1 a 7 to a 0 2 l t l t a 7 to a 0 3 t 4 7 t keep keep input/output port p5 7 to p5 0 1 l t l t a 15 to a 8 a 15 to a 8 2 t t * 6 * 5 t * 6 addr ess bus or input por t 3 l t t l t a 15 to a 8 4 t t * 6 * 5 t * 6 addr ess bus or input por t 7 keep keep input/output port (continued on next page) 465
table e-1 port state (cont) hardware port standby software bus program execution pin name mode reset mode standby mode sleep mode release mode state (normal operation) p6 3 to p6 0 1 a 19 to a 16 2 t 3 l t t l t a 19 to a 16 4 t t * 6 * 5 t * 6 addr ess bus or input por t 7 keep keep input/output port p7 7 to p7 0 1 2 3 t t keep * 2 keep keep input/output port 4 7 p8 7 to p8 0 1 2 3 t t t t t input port 4 7 p9 7 to p9 0 1 2 3 t t keep * 2 keep keep input/output port 4 7 h: high logic level l: low logic level t: high-impedance state keep: input ports are in the high-impedance state. output ports hold their previous output values. if ddr = 0 and dr = 1 in ports 5 and 6, the mos pull-ups remain on. * 1 the on-chip supporting modules are reset, so p1 7 becomes an input or output port controlled by ddr and dr. if p1 2 is programmed for back output, it goes to the high-impedance state. * 2 the on-chip supporting modules are reset, so these pins become input or output ports controlled by ddr and dr. * 3 breq can be received. back is high. * 4 back is low. * 5 address outputs are low. input ports are in the high-impedance state, or the mos pull-ups are on. * 6 pins used as input ports with the mos pull-up on (ddr = 0, dr = 1) do not go to the high- impedance state. the mos pull-up remains on. keep keep keep input/output port 466
table e-2 mos pull-up state port mode reset hardware standby mode other operating states* p5 7 to p5 0 1 off off off a 15 to a 8 2 on/off 3 off 4 on/off 7 p6 3 to p6 0 1 off off on/off a 19 to a 16 2 3 off 4 on/off 7 notes off: the mos pull-up is always off. on/off: the mos pull-up is on when ddr = 0 and dr = 1, and is off at other times. * including software standby mode. 467
e.2 pin states in reset state 1. mode 1 figure e-1 shows how the pin states change when the res pin goes low during external memory access in mode 1. as soon as res goes low, all ports are initialized to the input (high-impedance) state. the as, ds, rd, and wr signals all go high. the data bus (d 7 to d 0 ) is placed in the high-impedance state. the address bus and the r/w signal are initialized 1.5 ?clock periods after the low state of the res pin is sampled. all address bus signals are made low. the r/w signal is made high. the clock output pins p1 0 /?and p1 1 /e are initialized 0.5 ?clock periods after the low state of the res pin is sampled. both pins are initialized to the output state. 468
2. mode 2 figure e-4 shows how the pin states change when the res pin goes low during external memory access in mode 2. as soon as res goes low, all ports are initialized to the input (high-impedance) state. the as, ds, rd, and wr signals all go high. the data bus (d 7 to d 0 ) is placed in the high-impedance state. pins p5 7 /a 15 to p5 0 /a 8 of the address bus are initialized as input ports. a to a 15 0 res p1 / ? 0 internal reset signal r/w as, rd and ds (read) wr and ds (write) d to d (write) 7 0 i/o ports high impedance high impedance h?000 external memory access t 1 t 2 t 3 the dotted line indicates that p1 /?is an input port if the corresponding ddr bit is 0, but a clock output pin if the ddr bit is 1. * figure e-1 reset during memory access (mode 1) 469
pins a 7 to a 0 of the address bus and the r/w signal are initialized 1.5 ?clock periods after the low state of the res pin is sampled. pins a 7 to a 0 are made low . the r/w signal is made high. the clock output pins p1 0 /?and p1 1 /e are initialized 0.5 ?clock periods after the low state of the res pin is sampled. both pins are initialized to the output state. high impedance h?0 t 1 t 2 t 3 external memory access high impedance high impedance res p1 / ? 0 internal reset signal r/w as, rd and ds (read) wr and ds (write) d to d (write) 7 0 i/o ports a to a 7 0 p5 /a to p5 /a 7 15 0 8 the dotted line indicates that p1 /?is an input port if the corresponding ddr bit is 0, but a clock output pin if the ddr bit is 1. * 0 figure e-2 reset during memory access (mode 2) 470
3. mode 3 figure e-4 shows how the pin states change when the res pin goes low during external memory access in mode 3. as soon as res goes low, all ports are initialized to the input (high-impedance) state. the as, ds, rd, and wr signals all go high. the data bus (d 7 to d 0 ) is placed in the high-impedance state. the address bus and the r/w signal are initialized 1.5 ?clock periods after the low state of the res pin is sampled. all address bus signals are made low. the r/w signal is made high. the clock output pins p1 0 /?and p1 1 /e are initialized 0.5 ?clock periods after the low state of the res pin is sampled. both pins are initialized to the output state. 471
4. mode 4 figure e-4 shows how the pin states change when the res pin goes low during external memory access in mode 4. as soon as res goes low, all ports are initialized to the input (high-impedance) state. the as, ds, rd, and wr signals all go high. the data bus (d 7 to d 0 ) is placed in the high-impedance state. pins p5 7 /a 15 to p5 0 /a 8 of the address bus and pins p6 3 /a 19 to p6 0 /a 16 of the page address bus are initialized as input ports. high impedance high impedance h?0000 t 1 t 2 external memory access a to a 19 0 res p1 / ? 0 internal reset signal r/w as, rd and ds (read) wr and ds (write) d to d (write) 7 0 i/o ports the dotted line indicates that p1 /?is an input port if the corresponding ddr bit is 0, but a clock output pin if the ddr bit is 1. * 0 figure e-3 reset during memory access (mode 3) 472
pins a 7 to a 0 of the address bus and the r/w signal are initialized 1.5 ?clock periods after the low state of the res pin is sampled. pins a 7 to a 0 are made low. the r/w signal is made high. the clock output pins p1 0 /?and p1 1 /e are initialized 0.5 ?clock periods after the low state of the res pin is sampled. both pins are initialized to the output state. t 1 t 2 t 3 t 1 h?0 high impedance high impedance high impedance res p1 / ? 0 internal reset signal r/w as, rd and ds (read) wr and ds (write) d to d (write) 7 0 i/o ports a to a 7 0 p6 /a to p6 /a and 3 19 0 16 p5 /a to p5 /a 7 15 0 8 the dotted line indicates that p1 /?is an input port if the corresponding ddr bit is 0, but a clock output pin if the ddr bit is 1. * 0 figure e-4 reset during memory access (mode 4) 473
5. mode 7 figure e-5 shows how the pin states change when the res pin goes low in mode 7. as soon as res goes low, all ports are initialized to the input (high-impedance) state. the clock output pins p1 0 /?and p1 1 /e are initialized 0.5 ?clock periods after the low state of the res pin is sampled. both pins are initialized to the output state. high impedance res p1 / ? 0 internal reset signal i/o ports p1 / e* 0 the dotted line indicates that p1 /?and p1 /e are input ports if the corresponding ddr bit is 0, but clock output pins if the ddr bit is 1. * 0 0 figure e-5 reset during memory access (mode 7) 474
appendix f timing of transition to and recovery from hardware standby mode timing of transition to hardware standby mode (1) to retain ram contents when the rame bit in ramcr is set to 1, drive the res signal line low 10 system clock cycles before the stby signal, at a time when ram is not being accessed. (2) when the rame bit in ramcr is cleared to 0, or when it is not necessary to retain ram contents, res need not be driven low as in (1). timing of exit from hardware standby mode drive the res signal line low approximately 100 ns before the rise of the stby signal. res stby t 10 t 1 cyc fig. p437 upper t 0 ns 2 res stby t 100 ns t osc fig. p437 lower 475
appendix g package dimensions figure g-1 shows the dimensions of the cp-84 package. figure g-2 shows the dimensions of the cg-84 package. figure g-3 shows the dimensions of the fp-80a package. 1.27 0.42 ?0.10 29.28 28.20 ?0.50 28.20 ?0.50 4.40 ?0.20 2.55 ?0.15 0.10 30.23 ?0.12 53 33 54 74 75 84 1 11 12 32 30.23 ?0.12 0.75 29.21 ?0.38 2.16 1.27 12 32 11 33 1 84 75 53 74 54 1.27 0.635 4.03 max f d figure g-1 package dimensions (cp-84) figure g-2 package dimensions (cg-84) 476
60 0 ?5 0.10 0.12 m 17.2 ?0.3 41 61 80 1 20 40 21 17.2 ?.3 0.30 ?.10 0.65 3.05 max 0.10 1.60 0.80 ?0.30 14.0 2.70 +0.20 ?.16 0.17 +0.08 ?.05 figure g-3 package dimensions (fp-80a) 0.10 m 0.10 0.50 ?0.10 0 ?5 1.20 max 0.00 min 0.20 max 14.0 ?0.2 0.50 12.0 14.0 ?0.2 60 41 1 20 80 61 21 40 0.17 ?0.05 1.00 0.20 ?0.05 figure g-4 package dimensions (tfp-80c) 477

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